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backport D101773 to fix an llvm ir issue on mipsel in mips/mips-D101773-reloc.patch (Closes: #988965)
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@ -1,3 +1,15 @@
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llvm-toolchain-12 (1:12.0.1~++20210528111127+328a6ec95532-1~exp1) UNRELEASED; urgency=medium
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* experimental New snapshot release
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-- Sylvestre Ledru <sylvestre@debian.org> Fri, 28 May 2021 23:14:58 +0200
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llvm-toolchain-12 (1:12.0.1-rc1) unstable; urgency=medium
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* New testing upstream release
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-- Sylvestre Ledru <sylvestre@debian.org> Wed, 26 May 2021 12:45:40 +0200
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llvm-toolchain-12 (1:12.0.1~+rc1-1~exp2) UNRELEASED; urgency=medium
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[ John Paul Adrian Glaubitz ]
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@ -8,6 +20,10 @@ llvm-toolchain-12 (1:12.0.1~+rc1-1~exp2) UNRELEASED; urgency=medium
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* Add -fvisibility-inlines-hidden -Bsymbolic-functions -fno-semantic-interposition
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to the args to make clang faster
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See https://github.com/ClangBuiltLinux/tc-build/issues/150#issuecomment-849935207
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* backport D101773 to fix an llvm ir issue on mipsel
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in mips/mips-D101773-reloc.patch
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thanks to Ximin Luo
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(Closes: #988965)
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-- Sylvestre Ledru <sylvestre@debian.org> Fri, 28 May 2021 10:53:08 +0200
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75
debian/patches/mips/mips-D101773-reloc.patch
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From ab40c027f0ce9492919a72ad339de40bdb84b354 Mon Sep 17 00:00:00 2001
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From: Dimitry Andric <dimitry@andric.com>
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Date: Mon, 3 May 2021 20:08:49 +0200
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Subject: [PATCH] [MC][ELF] Work around R_MIPS_LO16 relocation handling problem
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This fixes PR49821, and avoids "ld.lld: error: test.o:(.rodata.str1.1):
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offset is outside the section" errors when linking MIPS objects with
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negative R_MIPS_LO16 implicit addends.
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ld.lld handles R_MIPS_HI16/R_MIPS_LO16 separately, not as a whole, so it
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doesn't know that an R_MIPS_HI16 with implicit addend 1 and an
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R_MIPS_LO16 with implicit addend -32768 represents 32768, which is in
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range of a MergeInputSection. We could introduce a new RelExpr member
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(like R_RISCV_PC_INDIRECT for R_RISCV_PCREL_HI20 / R_RISCV_PCREL_LO12)
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but the complexity is unnecessary given that GNU as keeps the original
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symbol for this case as well.
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Reviewed By: atanasyan, MaskRay
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Differential Revision: https://reviews.llvm.org/D101773
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---
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llvm/lib/MC/ELFObjectWriter.cpp | 11 +++++++++++
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llvm/test/MC/Mips/mips_lo16.s | 22 ++++++++++++++++++++++
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2 files changed, 33 insertions(+)
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create mode 100644 llvm/test/MC/Mips/mips_lo16.s
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Index: llvm-toolchain-12_12.0.1~+rc1/llvm/lib/MC/ELFObjectWriter.cpp
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===================================================================
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--- llvm-toolchain-12_12.0.1~+rc1.orig/llvm/lib/MC/ELFObjectWriter.cpp
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+++ llvm-toolchain-12_12.0.1~+rc1/llvm/lib/MC/ELFObjectWriter.cpp
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@@ -1397,6 +1397,17 @@ bool ELFObjectWriter::shouldRelocateWith
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if (TargetObjectWriter->getEMachine() == ELF::EM_386 &&
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Type == ELF::R_386_GOTOFF)
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return true;
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+
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+ // ld.lld handles R_MIPS_HI16/R_MIPS_LO16 separately, not as a whole, so
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+ // it doesn't know that an R_MIPS_HI16 with implicit addend 1 and an
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+ // R_MIPS_LO16 with implicit addend -32768 represents 32768, which is in
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+ // range of a MergeInputSection. We could introduce a new RelExpr member
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+ // (like R_RISCV_PC_INDIRECT for R_RISCV_PCREL_HI20 / R_RISCV_PCREL_LO12)
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+ // but the complexity is unnecessary given that GNU as keeps the original
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+ // symbol for this case as well.
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+ if (TargetObjectWriter->getEMachine() == ELF::EM_MIPS &&
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+ !hasRelocationAddend())
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+ return true;
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}
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// Most TLS relocations use a got, so they need the symbol. Even those that
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Index: llvm-toolchain-12_12.0.1~+rc1/llvm/test/MC/Mips/mips_lo16.s
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===================================================================
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--- /dev/null
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+++ llvm-toolchain-12_12.0.1~+rc1/llvm/test/MC/Mips/mips_lo16.s
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@@ -0,0 +1,22 @@
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+# PR49821: Check that R_MIPS_LO16 relocs do not wrap around with large addends.
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+
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+# RUN: llvm-mc %s -triple mips-unknown-unknown -filetype=obj | \
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+# RUN: llvm-objdump -d -r --no-show-raw-insn - | \
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+# RUN: FileCheck -check-prefix=MIPS32 %s
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+
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+# RUN: llvm-mc %s -triple mips64-unknown-unknown -filetype=obj | \
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+# RUN: llvm-objdump -d -r --no-show-raw-insn - | \
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+# RUN: FileCheck -check-prefix=MIPS64 %s
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+
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+ .text
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+foo:
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+ lui $2, %hi(bar)
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+# MIPS32: 00000000: R_MIPS_HI16 bar
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+# MIPS64: 0000000000000000: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE .rodata.str1.1+0x8000
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+ addiu $2, $2, %lo(bar)
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+# MIPS32: 00000004: R_MIPS_LO16 bar
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+# MIPS64: 0000000000000004: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE .rodata.str1.1+0x8000
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+ .section .rodata.str1.1,"aMS",@progbits,1
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+ .zero 0x8000
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+bar:
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+ .asciz "hello"
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1
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1
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@ -83,6 +83,7 @@ libcxx/libcxx-silent-failure-arm64.diff
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# Change default optims
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mips/mips-fpxx-enable.diff
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mips/mips-force-nomadd4.patch
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mips/mips-D101773-reloc.patch
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26-set-correct-float-abi.diff
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clang-baseline-fix-i386.patch
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