diff --git a/debian/changelog b/debian/changelog index 2cd2c439..538538c3 100644 --- a/debian/changelog +++ b/debian/changelog @@ -138,7 +138,85 @@ llvm-toolchain-snapshot (1:10~svn366440-1~exp1) experimental; urgency=medium -- Sylvestre Ledru Thu, 18 Jul 2019 18:58:32 +0200 -llvm-toolchain-9 (1:9.0.0-4) UNRELEASED; urgency=medium +llvm-toolchain-9 (1:9.0.1-2) unstable; urgency=medium + + [ James Clarke ] + * Include upstream patch D71028 for rust mips tests (Closes: #946874) + + [ Aurelien Jarno ] + * Include upstream patch D60657 for rust support on riscv64. + + -- James Clarke Fri, 20 Dec 2019 18:30:29 +0000 + +llvm-toolchain-9 (1:9.0.1-1) unstable; urgency=medium + + * New stable release + + -- Sylvestre Ledru Thu, 19 Dec 2019 13:48:21 +0100 + +llvm-toolchain-9 (1:9.0.1~+rc3-2) unstable; urgency=medium + + * Team upload. + [ Gianfranco Costamagna ] + * Commit Breaks/Replaces into git + + [ Julian Andres Klode ] + * Fix llvm-9-tools Breaks/Replaces libclang-common-9-dev (<< 1:9.0.1~+rc2) + (Closes: #946473) + + -- Gianfranco Costamagna Thu, 19 Dec 2019 00:26:04 +0100 + +llvm-toolchain-9 (1:9.0.1~+rc3-1) unstable; urgency=medium + + [ Sylvestre Ledru ] + * New snapshot release + upload to unstable + * Use secure URI in debian/watch. + * Move source package lintian overrides to debian/source. + * Remove patches force-gcc-header-obj.diff, hurd-pathmax.diff, impl- + path-hurd.diff, libcxxabi-arm-ehabi-fix.patch, libcxxabi-test-don-t- + fail-extended-long-double.patch, revert-change-soname.diff, try-to- + unbreak-thinlto.diff that are missing from debian/patches/series. + * Rely on pre-initialized dpkg-architecture variables. + * Move transitional package libclang-cpp1-9 to oldlibs/optional per + policy 4.0.1. + + [ Aurelien Jarno ] + * llvm-riscv64-fix-cffi.diff: backport patch to fix CFI directives on + riscv64 from master. + + -- Sylvestre Ledru Sat, 14 Dec 2019 12:43:17 +0100 + +llvm-toolchain-9 (1:9.0.1~+rc2-1~exp1) experimental; urgency=medium + + * New snapshot release + * Fix some paths, upstream moved from site-packages + to dist-packages for python packages + * Move yaml-bench from libclang-common-X.Y-dev to llvm-X.Y-tools where + it belongs + See http://lists.llvm.org/pipermail/llvm-dev/2019-December/137337.html + * Add a project in the cmake-test to silent a warning + (Closes: #945489) + + -- Sylvestre Ledru Tue, 03 Dec 2019 07:56:16 +0100 + +llvm-toolchain-9 (1:9.0.1~+rc1-1~exp1) experimental; urgency=medium + + * New snapshot release + + -- Sylvestre Ledru Sun, 24 Nov 2019 14:51:29 +0100 + +llvm-toolchain-9 (1:9.0.0-5) UNRELEASED; urgency=medium + + [ Gianfranco Costamagna ] + * Patch cmake files to disable the z3 support in Ubuntu + * Simplify rules file to put -g1 everywhere + + [ Sylvestre Ledru ] + * Add a project in the cmake-test to silent a warning (Closes: #945489) + + -- Gianfranco Costamagna Tue, 26 Nov 2019 09:24:38 +0100 + +llvm-toolchain-9 (1:9.0.0-4) unstable; urgency=medium [ Samuel Thibault ] * hurd-cxx-paths.diff: Re-introduce patch to find C++ headers. diff --git a/debian/control b/debian/control index 821e9fb3..8bde0248 100644 --- a/debian/control +++ b/debian/control @@ -169,7 +169,6 @@ Description: Clang library - Common development package Package: libclang-cpp1-10 Depends: libclang-cpp10, ${misc:Depends} Architecture: all -Priority: optional Section: oldlibs Description: transitional package This is a transitional package. It can safely be removed. @@ -339,6 +338,9 @@ Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends}, python, python3, python-pygments, python-yaml, python3-pygments, python3-yaml, +# Because of yaml-bench +Breaks: libclang-common-10-dev (<< 10~+201911120943210600592dd459242-1~exp2) +Replaces: libclang-common-10-dev (<< 10~+201911120943210600592dd459242-1~exp2) Description: Modular compiler and toolchain technologies, tools LLVM is a collection of libraries and tools that make it easy to build compilers, optimizers, just-in-time code generators, and many other diff --git a/debian/libclang-common-X.Y-dev.install.in b/debian/libclang-common-X.Y-dev.install.in index 0a1c7d11..4514f2cd 100644 --- a/debian/libclang-common-X.Y-dev.install.in +++ b/debian/libclang-common-X.Y-dev.install.in @@ -4,8 +4,4 @@ usr/lib/llvm-@LLVM_VERSION@/lib/clang/@LLVM_VERSION@*/lib usr/lib/llvm-@LLVM_VERSION@/lib/clang/@LLVM_VERSION@*/*.txt usr/lib/llvm-@LLVM_VERSION@/lib/clang/@LLVM_VERSION@*/share/*.txt -usr/lib/llvm-@LLVM_VERSION@/bin/yaml-bench - -usr/bin/yaml-bench-@LLVM_VERSION@ - diff --git a/debian/liblldb-7.install.kfreebsd b/debian/liblldb-7.install.kfreebsd deleted file mode 100644 index 231e7242..00000000 --- a/debian/liblldb-7.install.kfreebsd +++ /dev/null @@ -1,2 +0,0 @@ -usr/lib/llvm-7/lib/liblldb-7.so.1 /usr/lib/i386-kfreebsd-gnu/ -#usr/lib/llvm-7/lib/python2.7/site-packages/readline.so diff --git a/debian/liblldb-X.Y.install.in b/debian/liblldb-X.Y.install.in index c84bf430..24fa4446 100644 --- a/debian/liblldb-X.Y.install.in +++ b/debian/liblldb-X.Y.install.in @@ -1,4 +1,3 @@ usr/lib/llvm-@LLVM_VERSION@/lib/liblldb-@LLVM_VERSION@.so.1 /usr/lib/@DEB_HOST_MULTIARCH@/ -#usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/site-packages/readline.so usr/lib/llvm-@LLVM_VERSION@/lib/liblldbIntelFeatures.so.* diff --git a/debian/llvm-X.Y-dev.install.in b/debian/llvm-X.Y-dev.install.in index e5e3fc65..a6acd028 100644 --- a/debian/llvm-X.Y-dev.install.in +++ b/debian/llvm-X.Y-dev.install.in @@ -29,4 +29,3 @@ llvm/utils/vim/llvm-@LLVM_VERSION@-vimrc usr/share/vim/addons llvm/utils/emacs/emacs.el usr/share/emacs/site-lisp/llvm-@LLVM_VERSION@/ llvm/utils/emacs/llvm-mode.el usr/share/emacs/site-lisp/llvm-@LLVM_VERSION@/ llvm/utils/emacs/tablegen-mode.el usr/share/emacs/site-lisp/llvm-@LLVM_VERSION@/ - diff --git a/debian/llvm-X.Y-tools.install.in b/debian/llvm-X.Y-tools.install.in index fed288a2..0ceef3f4 100644 --- a/debian/llvm-X.Y-tools.install.in +++ b/debian/llvm-X.Y-tools.install.in @@ -2,6 +2,7 @@ usr/lib/llvm-@LLVM_VERSION@/bin/count usr/lib/llvm-@LLVM_VERSION@/bin/FileCheck usr/lib/llvm-@LLVM_VERSION@/bin/not +usr/lib/llvm-@LLVM_VERSION@/bin/yaml-bench usr/lib/llvm-@LLVM_VERSION@/share/opt-viewer/opt-viewer.py usr/lib/llvm-@LLVM_VERSION@/share/opt-viewer/optrecord.py usr/lib/llvm-@LLVM_VERSION@/share/opt-viewer/style.css @@ -9,8 +10,10 @@ usr/lib/llvm-@LLVM_VERSION@/share/opt-viewer/opt-diff.py usr/lib/llvm-@LLVM_VERSION@/share/opt-viewer/optpmap.py usr/lib/llvm-@LLVM_VERSION@/share/opt-viewer/opt-stats.py + llvm/utils/lit/* /usr/lib/llvm-@LLVM_VERSION@/build/utils/lit/ usr/bin/count-@LLVM_VERSION@ usr/bin/FileCheck-@LLVM_VERSION@ usr/bin/not-@LLVM_VERSION@ +usr/bin/yaml-bench-@LLVM_VERSION@ diff --git a/debian/orig-tar.sh b/debian/orig-tar.sh index fa5f9984..8cc6e9e4 100755 --- a/debian/orig-tar.sh +++ b/debian/orig-tar.sh @@ -127,7 +127,7 @@ else fi git_tag="llvmorg-$EXACT_VERSION" VERSION=$EXACT_VERSION - if test -n "$TAG" -a -z "$FINAL_RELEASE"; then + if test -n "$TAG"; then git_tag="$git_tag-$TAG" VERSION="$VERSION~+$TAG" fi diff --git a/debian/patches/D60657-riscv-pcrel_lo.diff b/debian/patches/D60657-riscv-pcrel_lo.diff new file mode 100644 index 00000000..b609bd22 --- /dev/null +++ b/debian/patches/D60657-riscv-pcrel_lo.diff @@ -0,0 +1,126 @@ +commit 41449c58c58e466bcf9cdc4f7415950382bad8d7 +Author: Roger Ferrer Ibanez +Date: Fri Nov 8 08:26:30 2019 +0000 + + [RISCV] Fix evaluation of %pcrel_lo + + The following testcase + + function: + .Lpcrel_label1: + auipc a0, %pcrel_hi(other_function) + addi a1, a0, %pcrel_lo(.Lpcrel_label1) + .p2align 2 # Causes a new fragment to be emitted + + .type other_function,@function + other_function: + ret + + exposes an odd behaviour in which only the %pcrel_hi relocation is + evaluated but not the %pcrel_lo. + + $ llvm-mc -triple riscv64 -filetype obj t.s | llvm-objdump -d -r - + + : file format ELF64-riscv + + Disassembly of section .text: + 0000000000000000 function: + 0: 17 05 00 00 auipc a0, 0 + 4: 93 05 05 00 mv a1, a0 + 0000000000000004: R_RISCV_PCREL_LO12_I other_function+4 + + 0000000000000008 other_function: + 8: 67 80 00 00 ret + + The reason seems to be that in RISCVAsmBackend::shouldForceRelocation we + only consider the fragment but in RISCVMCExpr::evaluatePCRelLo we + consider the section. This usually works but there are cases where the + section may still be the same but the fragment may be another one. In + that case we end forcing a %pcrel_lo relocation without any %pcrel_hi. + + This patch makes RISCVAsmBackend::shouldForceRelocation use the section, + if any, to determine if the relocation must be forced or not. + + Differential Revision: https://reviews.llvm.org/D60657 + +diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +index f6b727ae37c..5881a0a86ef 100644 +--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp ++++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +@@ -64,11 +64,15 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm, + case RISCV::fixup_riscv_tls_gd_hi20: + ShouldForce = true; + break; +- case RISCV::fixup_riscv_pcrel_hi20: +- ShouldForce = T->getValue()->findAssociatedFragment() != +- Fixup.getValue()->findAssociatedFragment(); ++ case RISCV::fixup_riscv_pcrel_hi20: { ++ MCFragment *TFragment = T->getValue()->findAssociatedFragment(); ++ MCFragment *FixupFragment = Fixup.getValue()->findAssociatedFragment(); ++ assert(FixupFragment && "We should have a fragment for this fixup"); ++ ShouldForce = ++ !TFragment || TFragment->getParent() != FixupFragment->getParent(); + break; + } ++ } + break; + } + +diff --git a/llvm/test/MC/RISCV/pcrel-fixups.s b/llvm/test/MC/RISCV/pcrel-fixups.s +new file mode 100644 +index 00000000000..1025988967a +--- /dev/null ++++ b/llvm/test/MC/RISCV/pcrel-fixups.s +@@ -0,0 +1,52 @@ ++# RUN: llvm-mc -triple riscv32 -mattr=-relax -filetype obj %s \ ++# RUN: | llvm-objdump -M no-aliases -d -r - \ ++# RUN: | FileCheck --check-prefix NORELAX %s ++# RUN: llvm-mc -triple riscv32 -mattr=+relax -filetype obj %s \ ++# RUN: | llvm-objdump -M no-aliases -d -r - \ ++# RUN: | FileCheck --check-prefix RELAX %s ++# RUN: llvm-mc -triple riscv64 -mattr=-relax -filetype obj %s \ ++# RUN: | llvm-objdump -M no-aliases -d -r - \ ++# RUN: | FileCheck --check-prefix NORELAX %s ++# RUN: llvm-mc -triple riscv64 -mattr=+relax -filetype obj %s \ ++# RUN: | llvm-objdump -M no-aliases -d -r - \ ++# RUN: | FileCheck --check-prefix RELAX %s ++ ++# Fixups for %pcrel_hi / %pcrel_lo can be evaluated within a section, ++# regardless of the fragment containing the target address. ++ ++function: ++.Lpcrel_label1: ++ auipc a0, %pcrel_hi(other_function) ++ addi a1, a0, %pcrel_lo(.Lpcrel_label1) ++# NORELAX: auipc a0, 0 ++# NORELAX-NOT: R_RISCV ++# NORELAX: addi a1, a0, 16 ++# NORELAX-NOT: R_RISCV ++ ++# RELAX: auipc a0, 0 ++# RELAX: R_RISCV_PCREL_HI20 other_function ++# RELAX: R_RISCV_RELAX *ABS* ++# RELAX: addi a1, a0, 0 ++# RELAX: R_RISCV_PCREL_LO12_I .Lpcrel_label1 ++# RELAX: R_RISCV_RELAX *ABS* ++ ++ .p2align 2 # Cause a new fragment be emitted here ++.Lpcrel_label2: ++ auipc a0, %pcrel_hi(other_function) ++ addi a1, a0, %pcrel_lo(.Lpcrel_label2) ++# NORELAX: auipc a0, 0 ++# NORELAX-NOT: R_RISCV ++# NORELAX: addi a1, a0, 8 ++# NORELAX-NOT: R_RISCV ++ ++# RELAX: auipc a0, 0 ++# RELAX: R_RISCV_PCREL_HI20 other_function ++# RELAX: R_RISCV_RELAX *ABS* ++# RELAX: addi a1, a0, 0 ++# RELAX: R_RISCV_PCREL_LO12_I .Lpcrel_label2 ++# RELAX: R_RISCV_RELAX *ABS* ++ ++ .type other_function,@function ++other_function: ++ ret ++ diff --git a/debian/patches/D71028-mips-rust-test.diff b/debian/patches/D71028-mips-rust-test.diff new file mode 100644 index 00000000..bcbb966c --- /dev/null +++ b/debian/patches/D71028-mips-rust-test.diff @@ -0,0 +1,5529 @@ +From d7357c52a40a136f25c1cf5ae31a699d51885e49 Mon Sep 17 00:00:00 2001 +From: Mirko Brkusanin +Date: Thu, 12 Dec 2019 11:19:41 +0100 +Subject: [PATCH] [Mips] Add support for min/max/umin/umax atomics + +In order to properly implement these atomic we need one register more than other +binary atomics. It is used for storing result from comparing values in addition +to the one that is used for actual result of operation. + +https://reviews.llvm.org/D71028 + +Changed-by: James Clarke +[Backported to 9 by replacing Register with unsigned] +--- + llvm/lib/Target/Mips/Mips64InstrInfo.td | 9 + + llvm/lib/Target/Mips/MipsExpandPseudo.cpp | 219 +- + llvm/lib/Target/Mips/MipsISelLowering.cpp | 154 +- + llvm/lib/Target/Mips/MipsInstrInfo.td | 25 + + llvm/lib/Target/Mips/MipsScheduleGeneric.td | 3 +- + llvm/lib/Target/Mips/MipsScheduleP5600.td | 3 +- + llvm/test/CodeGen/Mips/atomic-min-max-64.ll | 158 + + llvm/test/CodeGen/Mips/atomic-min-max.ll | 4674 +++++++++++++++++++ + llvm/test/CodeGen/Mips/atomic.ll | 2 +- + 9 files changed, 5218 insertions(+), 29 deletions(-) + create mode 100644 llvm/test/CodeGen/Mips/atomic-min-max-64.ll + create mode 100644 llvm/test/CodeGen/Mips/atomic-min-max.ll + +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/Mips64InstrInfo.td +=================================================================== +--- llvm-toolchain-9-9.0.1~+rc3.orig/llvm/lib/Target/Mips/Mips64InstrInfo.td ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/Mips64InstrInfo.td +@@ -82,6 +82,10 @@ let usesCustomInserter = 1 in { + def ATOMIC_LOAD_NAND_I64 : Atomic2Ops; + def ATOMIC_SWAP_I64 : Atomic2Ops; + def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap; ++ def ATOMIC_LOAD_MIN_I64 : Atomic2Ops; ++ def ATOMIC_LOAD_MAX_I64 : Atomic2Ops; ++ def ATOMIC_LOAD_UMIN_I64 : Atomic2Ops; ++ def ATOMIC_LOAD_UMAX_I64 : Atomic2Ops; + } + + def ATOMIC_LOAD_ADD_I64_POSTRA : Atomic2OpsPostRA; +@@ -95,6 +99,11 @@ def ATOMIC_SWAP_I64_POSTRA : Atomic + + def ATOMIC_CMP_SWAP_I64_POSTRA : AtomicCmpSwapPostRA; + ++def ATOMIC_LOAD_MIN_I64_POSTRA : Atomic2OpsPostRA; ++def ATOMIC_LOAD_MAX_I64_POSTRA : Atomic2OpsPostRA; ++def ATOMIC_LOAD_UMIN_I64_POSTRA : Atomic2OpsPostRA; ++def ATOMIC_LOAD_UMAX_I64_POSTRA : Atomic2OpsPostRA; ++ + /// Pseudo instructions for loading and storing accumulator registers. + let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { + def LOAD_ACC128 : Load<"", ACC128>; +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsExpandPseudo.cpp +=================================================================== +--- llvm-toolchain-9-9.0.1~+rc3.orig/llvm/lib/Target/Mips/MipsExpandPseudo.cpp ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsExpandPseudo.cpp +@@ -308,7 +308,7 @@ bool MipsExpandPseudo::expandAtomicBinOp + const bool ArePtrs64bit = STI->getABI().ArePtrs64bit(); + DebugLoc DL = I->getDebugLoc(); + +- unsigned LL, SC; ++ unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; + unsigned BEQ = Mips::BEQ; + unsigned SEOp = Mips::SEH; + +@@ -316,15 +316,32 @@ bool MipsExpandPseudo::expandAtomicBinOp + LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; + SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; + BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; ++ SLT = Mips::SLT_MM; ++ SLTu = Mips::SLTu_MM; ++ OR = STI->hasMips32r6() ? Mips::OR_MMR6 : Mips::OR_MM; ++ MOVN = Mips::MOVN_I_MM; ++ MOVZ = Mips::MOVZ_I_MM; ++ SELNEZ = STI->hasMips32r6() ? Mips::SELNEZ_MMR6 : Mips::SELNEZ; ++ SELEQZ = STI->hasMips32r6() ? Mips::SELEQZ_MMR6 : Mips::SELEQZ; + } else { + LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) + : (ArePtrs64bit ? Mips::LL64 : Mips::LL); + SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) + : (ArePtrs64bit ? Mips::SC64 : Mips::SC); ++ SLT = Mips::SLT; ++ SLTu = Mips::SLTu; ++ OR = Mips::OR; ++ MOVN = Mips::MOVN_I_I; ++ MOVZ = Mips::MOVZ_I_I; ++ SELNEZ = Mips::SELNEZ; ++ SELEQZ = Mips::SELEQZ; + } + + bool IsSwap = false; + bool IsNand = false; ++ bool IsMin = false; ++ bool IsMax = false; ++ bool IsUnsigned = false; + + unsigned Opcode = 0; + switch (I->getOpcode()) { +@@ -370,6 +387,22 @@ bool MipsExpandPseudo::expandAtomicBinOp + case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: + Opcode = Mips::XOR; + break; ++ case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: ++ case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: ++ IsUnsigned = true; ++ LLVM_FALLTHROUGH; ++ case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: ++ case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: ++ IsMin = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: ++ case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: ++ IsUnsigned = true; ++ LLVM_FALLTHROUGH; ++ case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: ++ case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: ++ IsMax = true; ++ break; + default: + llvm_unreachable("Unknown subword atomic pseudo for expansion!"); + } +@@ -415,6 +448,68 @@ bool MipsExpandPseudo::expandAtomicBinOp + BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes) + .addReg(BinOpRes) + .addReg(Mask); ++ } else if (IsMin || IsMax) { ++ ++ assert(I->getNumOperands() == 10 && ++ "Atomics min|max|umin|umax use an additional register"); ++ unsigned Scratch4 = I->getOperand(9).getReg(); ++ ++ unsigned SLTScratch4 = IsUnsigned ? SLTu : SLT; ++ unsigned SELIncr = IsMax ? SELNEZ : SELEQZ; ++ unsigned SELOldVal = IsMax ? SELEQZ : SELNEZ; ++ unsigned MOVIncr = IsMax ? MOVN : MOVZ; ++ ++ // For little endian we need to clear uninterested bits. ++ if (STI->isLittle()) { ++ // and OldVal, OldVal, Mask ++ // and Incr, Incr, Mask ++ BuildMI(loopMBB, DL, TII->get(Mips::AND), OldVal) ++ .addReg(OldVal) ++ .addReg(Mask); ++ BuildMI(loopMBB, DL, TII->get(Mips::AND), Incr).addReg(Incr).addReg(Mask); ++ } ++ ++ // unsigned: sltu Scratch4, oldVal, Incr ++ // signed: slt Scratch4, oldVal, Incr ++ BuildMI(loopMBB, DL, TII->get(SLTScratch4), Scratch4) ++ .addReg(OldVal) ++ .addReg(Incr); ++ ++ if (STI->hasMips64r6() || STI->hasMips32r6()) { ++ // max: seleqz BinOpRes, OldVal, Scratch4 ++ // selnez Scratch4, Incr, Scratch4 ++ // or BinOpRes, BinOpRes, Scratch4 ++ // min: selnqz BinOpRes, OldVal, Scratch4 ++ // seleqz Scratch4, Incr, Scratch4 ++ // or BinOpRes, BinOpRes, Scratch4 ++ BuildMI(loopMBB, DL, TII->get(SELOldVal), BinOpRes) ++ .addReg(OldVal) ++ .addReg(Scratch4); ++ BuildMI(loopMBB, DL, TII->get(SELIncr), Scratch4) ++ .addReg(Incr) ++ .addReg(Scratch4); ++ BuildMI(loopMBB, DL, TII->get(OR), BinOpRes) ++ .addReg(BinOpRes) ++ .addReg(Scratch4); ++ } else { ++ // max: move BinOpRes, OldVal ++ // movn BinOpRes, Incr, Scratch4, BinOpRes ++ // min: move BinOpRes, OldVal ++ // movz BinOpRes, Incr, Scratch4, BinOpRes ++ BuildMI(loopMBB, DL, TII->get(OR), BinOpRes) ++ .addReg(OldVal) ++ .addReg(Mips::ZERO); ++ BuildMI(loopMBB, DL, TII->get(MOVIncr), BinOpRes) ++ .addReg(Incr) ++ .addReg(Scratch4) ++ .addReg(BinOpRes); ++ } ++ ++ // and BinOpRes, BinOpRes, Mask ++ BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes) ++ .addReg(BinOpRes) ++ .addReg(Mask); ++ + } else if (!IsSwap) { + // binopres, oldval, incr2 + // and newval, binopres, mask +@@ -488,13 +583,20 @@ bool MipsExpandPseudo::expandAtomicBinOp + const bool ArePtrs64bit = STI->getABI().ArePtrs64bit(); + DebugLoc DL = I->getDebugLoc(); + +- unsigned LL, SC, ZERO, BEQ; ++ unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; + + if (Size == 4) { + if (STI->inMicroMipsMode()) { + LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; + SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; + BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; ++ SLT = Mips::SLT_MM; ++ SLTu = Mips::SLTu_MM; ++ OR = STI->hasMips32r6() ? Mips::OR_MMR6 : Mips::OR_MM; ++ MOVN = Mips::MOVN_I_MM; ++ MOVZ = Mips::MOVZ_I_MM; ++ SELNEZ = STI->hasMips32r6() ? Mips::SELNEZ_MMR6 : Mips::SELNEZ; ++ SELEQZ = STI->hasMips32r6() ? Mips::SELEQZ_MMR6 : Mips::SELEQZ; + } else { + LL = STI->hasMips32r6() + ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) +@@ -503,6 +605,13 @@ bool MipsExpandPseudo::expandAtomicBinOp + ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) + : (ArePtrs64bit ? Mips::SC64 : Mips::SC); + BEQ = Mips::BEQ; ++ SLT = Mips::SLT; ++ SLTu = Mips::SLTu; ++ OR = Mips::OR; ++ MOVN = Mips::MOVN_I_I; ++ MOVZ = Mips::MOVZ_I_I; ++ SELNEZ = Mips::SELNEZ; ++ SELEQZ = Mips::SELEQZ; + } + + ZERO = Mips::ZERO; +@@ -511,6 +620,13 @@ bool MipsExpandPseudo::expandAtomicBinOp + SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; + ZERO = Mips::ZERO_64; + BEQ = Mips::BEQ64; ++ SLT = Mips::SLT64; ++ SLTu = Mips::SLTu64; ++ OR = Mips::OR64; ++ MOVN = Mips::MOVN_I64_I64; ++ MOVZ = Mips::MOVZ_I64_I64; ++ SELNEZ = Mips::SELNEZ64; ++ SELEQZ = Mips::SELEQZ64; + } + + unsigned OldVal = I->getOperand(0).getReg(); +@@ -519,10 +635,15 @@ bool MipsExpandPseudo::expandAtomicBinOp + unsigned Scratch = I->getOperand(3).getReg(); + + unsigned Opcode = 0; +- unsigned OR = 0; + unsigned AND = 0; + unsigned NOR = 0; ++ ++ bool IsOr = false; + bool IsNand = false; ++ bool IsMin = false; ++ bool IsMax = false; ++ bool IsUnsigned = false; ++ + switch (I->getOpcode()) { + case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: + Opcode = Mips::ADDu; +@@ -545,7 +666,7 @@ bool MipsExpandPseudo::expandAtomicBinOp + NOR = Mips::NOR; + break; + case Mips::ATOMIC_SWAP_I32_POSTRA: +- OR = Mips::OR; ++ IsOr = true; + break; + case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: + Opcode = Mips::DADDu; +@@ -568,7 +689,23 @@ bool MipsExpandPseudo::expandAtomicBinOp + NOR = Mips::NOR64; + break; + case Mips::ATOMIC_SWAP_I64_POSTRA: +- OR = Mips::OR64; ++ IsOr = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: ++ case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: ++ IsUnsigned = true; ++ LLVM_FALLTHROUGH; ++ case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: ++ case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: ++ IsMin = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: ++ case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: ++ IsUnsigned = true; ++ LLVM_FALLTHROUGH; ++ case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: ++ case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: ++ IsMax = true; + break; + default: + llvm_unreachable("Unknown pseudo atomic!"); +@@ -592,7 +729,59 @@ bool MipsExpandPseudo::expandAtomicBinOp + BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); + assert((OldVal != Ptr) && "Clobbered the wrong ptr reg!"); + assert((OldVal != Incr) && "Clobbered the wrong reg!"); +- if (Opcode) { ++ if (IsMin || IsMax) { ++ ++ assert(I->getNumOperands() == 5 && ++ "Atomics min|max|umin|umax use an additional register"); ++ unsigned Scratch2 = I->getOperand(4).getReg(); ++ ++ // On Mips64 result of slt is GPR32. ++ unsigned Scratch2_32 = ++ (Size == 8) ? STI->getRegisterInfo()->getSubReg(Scratch2, Mips::sub_32) ++ : Scratch2; ++ ++ unsigned SLTScratch2 = IsUnsigned ? SLTu : SLT; ++ unsigned SELIncr = IsMax ? SELNEZ : SELEQZ; ++ unsigned SELOldVal = IsMax ? SELEQZ : SELNEZ; ++ unsigned MOVIncr = IsMax ? MOVN : MOVZ; ++ ++ // unsigned: sltu Scratch2, oldVal, Incr ++ // signed: slt Scratch2, oldVal, Incr ++ BuildMI(loopMBB, DL, TII->get(SLTScratch2), Scratch2_32) ++ .addReg(OldVal) ++ .addReg(Incr); ++ ++ if (STI->hasMips64r6() || STI->hasMips32r6()) { ++ // max: seleqz Scratch, OldVal, Scratch2 ++ // selnez Scratch2, Incr, Scratch2 ++ // or Scratch, Scratch, Scratch2 ++ // min: selnez Scratch, OldVal, Scratch2 ++ // seleqz Scratch2, Incr, Scratch2 ++ // or Scratch, Scratch, Scratch2 ++ BuildMI(loopMBB, DL, TII->get(SELOldVal), Scratch) ++ .addReg(OldVal) ++ .addReg(Scratch2); ++ BuildMI(loopMBB, DL, TII->get(SELIncr), Scratch2) ++ .addReg(Incr) ++ .addReg(Scratch2); ++ BuildMI(loopMBB, DL, TII->get(OR), Scratch) ++ .addReg(Scratch) ++ .addReg(Scratch2); ++ } else { ++ // max: move Scratch, OldVal ++ // movn Scratch, Incr, Scratch2, Scratch ++ // min: move Scratch, OldVal ++ // movz Scratch, Incr, Scratch2, Scratch ++ BuildMI(loopMBB, DL, TII->get(OR), Scratch) ++ .addReg(OldVal) ++ .addReg(ZERO); ++ BuildMI(loopMBB, DL, TII->get(MOVIncr), Scratch) ++ .addReg(Incr) ++ .addReg(Scratch2) ++ .addReg(Scratch); ++ } ++ ++ } else if (Opcode) { + BuildMI(loopMBB, DL, TII->get(Opcode), Scratch).addReg(OldVal).addReg(Incr); + } else if (IsNand) { + assert(AND && NOR && +@@ -600,7 +789,7 @@ bool MipsExpandPseudo::expandAtomicBinOp + BuildMI(loopMBB, DL, TII->get(AND), Scratch).addReg(OldVal).addReg(Incr); + BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch); + } else { +- assert(OR && "Unknown instruction for atomic pseudo expansion!"); ++ assert(IsOr && OR && "Unknown instruction for atomic pseudo expansion!"); + BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO); + } + +@@ -644,6 +833,14 @@ bool MipsExpandPseudo::expandMI(MachineB + case Mips::ATOMIC_LOAD_OR_I16_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: ++ case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: ++ case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: ++ case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: ++ case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: ++ case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: ++ case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: ++ case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: ++ case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: + return expandAtomicBinOpSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: +@@ -652,6 +849,10 @@ bool MipsExpandPseudo::expandMI(MachineB + case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: + case Mips::ATOMIC_SWAP_I32_POSTRA: ++ case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: ++ case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: ++ case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: ++ case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 4); + case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: +@@ -660,6 +861,10 @@ bool MipsExpandPseudo::expandMI(MachineB + case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: + case Mips::ATOMIC_SWAP_I64_POSTRA: ++ case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: ++ case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: ++ case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: ++ case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 8); + default: + return Modified; +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsISelLowering.cpp +=================================================================== +--- llvm-toolchain-9-9.0.1~+rc3.orig/llvm/lib/Target/Mips/MipsISelLowering.cpp ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsISelLowering.cpp +@@ -1369,6 +1369,43 @@ MipsTargetLowering::EmitInstrWithCustomI + return emitAtomicCmpSwap(MI, BB); + case Mips::ATOMIC_CMP_SWAP_I64: + return emitAtomicCmpSwap(MI, BB); ++ ++ case Mips::ATOMIC_LOAD_MIN_I8: ++ return emitAtomicBinaryPartword(MI, BB, 1); ++ case Mips::ATOMIC_LOAD_MIN_I16: ++ return emitAtomicBinaryPartword(MI, BB, 2); ++ case Mips::ATOMIC_LOAD_MIN_I32: ++ return emitAtomicBinary(MI, BB); ++ case Mips::ATOMIC_LOAD_MIN_I64: ++ return emitAtomicBinary(MI, BB); ++ ++ case Mips::ATOMIC_LOAD_MAX_I8: ++ return emitAtomicBinaryPartword(MI, BB, 1); ++ case Mips::ATOMIC_LOAD_MAX_I16: ++ return emitAtomicBinaryPartword(MI, BB, 2); ++ case Mips::ATOMIC_LOAD_MAX_I32: ++ return emitAtomicBinary(MI, BB); ++ case Mips::ATOMIC_LOAD_MAX_I64: ++ return emitAtomicBinary(MI, BB); ++ ++ case Mips::ATOMIC_LOAD_UMIN_I8: ++ return emitAtomicBinaryPartword(MI, BB, 1); ++ case Mips::ATOMIC_LOAD_UMIN_I16: ++ return emitAtomicBinaryPartword(MI, BB, 2); ++ case Mips::ATOMIC_LOAD_UMIN_I32: ++ return emitAtomicBinary(MI, BB); ++ case Mips::ATOMIC_LOAD_UMIN_I64: ++ return emitAtomicBinary(MI, BB); ++ ++ case Mips::ATOMIC_LOAD_UMAX_I8: ++ return emitAtomicBinaryPartword(MI, BB, 1); ++ case Mips::ATOMIC_LOAD_UMAX_I16: ++ return emitAtomicBinaryPartword(MI, BB, 2); ++ case Mips::ATOMIC_LOAD_UMAX_I32: ++ return emitAtomicBinary(MI, BB); ++ case Mips::ATOMIC_LOAD_UMAX_I64: ++ return emitAtomicBinary(MI, BB); ++ + case Mips::PseudoSDIV: + case Mips::PseudoUDIV: + case Mips::DIV: +@@ -1430,6 +1467,7 @@ MipsTargetLowering::emitAtomicBinary(Mac + DebugLoc DL = MI.getDebugLoc(); + + unsigned AtomicOp; ++ bool NeedsAdditionalReg = false; + switch (MI.getOpcode()) { + case Mips::ATOMIC_LOAD_ADD_I32: + AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; +@@ -1473,6 +1511,38 @@ MipsTargetLowering::emitAtomicBinary(Mac + case Mips::ATOMIC_SWAP_I64: + AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; + break; ++ case Mips::ATOMIC_LOAD_MIN_I32: ++ AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_MAX_I32: ++ AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMIN_I32: ++ AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMAX_I32: ++ AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_MIN_I64: ++ AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_MAX_I64: ++ AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMIN_I64: ++ AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMAX_I64: ++ AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA; ++ NeedsAdditionalReg = true; ++ break; + default: + llvm_unreachable("Unknown pseudo atomic for replacement!"); + } +@@ -1525,12 +1595,19 @@ MipsTargetLowering::emitAtomicBinary(Mac + BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); + BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); + +- BuildMI(*BB, II, DL, TII->get(AtomicOp)) +- .addReg(OldVal, RegState::Define | RegState::EarlyClobber) +- .addReg(PtrCopy) +- .addReg(IncrCopy) +- .addReg(Scratch, RegState::Define | RegState::EarlyClobber | +- RegState::Implicit | RegState::Dead); ++ MachineInstrBuilder MIB = ++ BuildMI(*BB, II, DL, TII->get(AtomicOp)) ++ .addReg(OldVal, RegState::Define | RegState::EarlyClobber) ++ .addReg(PtrCopy) ++ .addReg(IncrCopy) ++ .addReg(Scratch, RegState::Define | RegState::EarlyClobber | ++ RegState::Implicit | RegState::Dead); ++ if (NeedsAdditionalReg) { ++ unsigned Scratch2 = ++ RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); ++ MIB.addReg(Scratch2, RegState::Define | RegState::EarlyClobber | ++ RegState::Implicit | RegState::Dead); ++ } + + MI.eraseFromParent(); + +@@ -1598,6 +1675,7 @@ MachineBasicBlock *MipsTargetLowering::e + unsigned Scratch3 = RegInfo.createVirtualRegister(RC); + + unsigned AtomicOp = 0; ++ bool NeedsAdditionalReg = false; + switch (MI.getOpcode()) { + case Mips::ATOMIC_LOAD_NAND_I8: + AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; +@@ -1641,6 +1719,38 @@ MachineBasicBlock *MipsTargetLowering::e + case Mips::ATOMIC_LOAD_XOR_I16: + AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; + break; ++ case Mips::ATOMIC_LOAD_MIN_I8: ++ AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_MIN_I16: ++ AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_MAX_I8: ++ AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_MAX_I16: ++ AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMIN_I8: ++ AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMIN_I16: ++ AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMAX_I8: ++ AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA; ++ NeedsAdditionalReg = true; ++ break; ++ case Mips::ATOMIC_LOAD_UMAX_I16: ++ AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA; ++ NeedsAdditionalReg = true; ++ break; + default: + llvm_unreachable("Unknown subword atomic pseudo for expansion!"); + } +@@ -1695,19 +1805,25 @@ MachineBasicBlock *MipsTargetLowering::e + // emitAtomicBinary. In summary, we need a scratch register which is going to + // be undef, that is unique among registers chosen for the instruction. + +- BuildMI(BB, DL, TII->get(AtomicOp)) +- .addReg(Dest, RegState::Define | RegState::EarlyClobber) +- .addReg(AlignedAddr) +- .addReg(Incr2) +- .addReg(Mask) +- .addReg(Mask2) +- .addReg(ShiftAmt) +- .addReg(Scratch, RegState::EarlyClobber | RegState::Define | +- RegState::Dead | RegState::Implicit) +- .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | +- RegState::Dead | RegState::Implicit) +- .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | +- RegState::Dead | RegState::Implicit); ++ MachineInstrBuilder MIB = ++ BuildMI(BB, DL, TII->get(AtomicOp)) ++ .addReg(Dest, RegState::Define | RegState::EarlyClobber) ++ .addReg(AlignedAddr) ++ .addReg(Incr2) ++ .addReg(Mask) ++ .addReg(Mask2) ++ .addReg(ShiftAmt) ++ .addReg(Scratch, RegState::EarlyClobber | RegState::Define | ++ RegState::Dead | RegState::Implicit) ++ .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | ++ RegState::Dead | RegState::Implicit) ++ .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | ++ RegState::Dead | RegState::Implicit); ++ if (NeedsAdditionalReg) { ++ unsigned Scratch4 = RegInfo.createVirtualRegister(RC); ++ MIB.addReg(Scratch4, RegState::EarlyClobber | RegState::Define | ++ RegState::Dead | RegState::Implicit); ++ } + + MI.eraseFromParent(); // The instruction is gone now. + +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsInstrInfo.td +=================================================================== +--- llvm-toolchain-9-9.0.1~+rc3.orig/llvm/lib/Target/Mips/MipsInstrInfo.td ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsInstrInfo.td +@@ -1973,6 +1973,18 @@ let usesCustomInserter = 1 in { + def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap; + def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap; + ++ def ATOMIC_LOAD_MIN_I8 : Atomic2Ops; ++ def ATOMIC_LOAD_MIN_I16 : Atomic2Ops; ++ def ATOMIC_LOAD_MIN_I32 : Atomic2Ops; ++ def ATOMIC_LOAD_MAX_I8 : Atomic2Ops; ++ def ATOMIC_LOAD_MAX_I16 : Atomic2Ops; ++ def ATOMIC_LOAD_MAX_I32 : Atomic2Ops; ++ def ATOMIC_LOAD_UMIN_I8 : Atomic2Ops; ++ def ATOMIC_LOAD_UMIN_I16 : Atomic2Ops; ++ def ATOMIC_LOAD_UMIN_I32 : Atomic2Ops; ++ def ATOMIC_LOAD_UMAX_I8 : Atomic2Ops; ++ def ATOMIC_LOAD_UMAX_I16 : Atomic2Ops; ++ def ATOMIC_LOAD_UMAX_I32 : Atomic2Ops; + } + + def ATOMIC_LOAD_ADD_I8_POSTRA : Atomic2OpsSubwordPostRA; +@@ -2002,6 +2014,19 @@ def ATOMIC_CMP_SWAP_I8_POSTRA : AtomicCm + def ATOMIC_CMP_SWAP_I16_POSTRA : AtomicCmpSwapSubwordPostRA; + def ATOMIC_CMP_SWAP_I32_POSTRA : AtomicCmpSwapPostRA; + ++def ATOMIC_LOAD_MIN_I8_POSTRA : Atomic2OpsSubwordPostRA; ++def ATOMIC_LOAD_MIN_I16_POSTRA : Atomic2OpsSubwordPostRA; ++def ATOMIC_LOAD_MIN_I32_POSTRA : Atomic2OpsPostRA; ++def ATOMIC_LOAD_MAX_I8_POSTRA : Atomic2OpsSubwordPostRA; ++def ATOMIC_LOAD_MAX_I16_POSTRA : Atomic2OpsSubwordPostRA; ++def ATOMIC_LOAD_MAX_I32_POSTRA : Atomic2OpsPostRA; ++def ATOMIC_LOAD_UMIN_I8_POSTRA : Atomic2OpsSubwordPostRA; ++def ATOMIC_LOAD_UMIN_I16_POSTRA : Atomic2OpsSubwordPostRA; ++def ATOMIC_LOAD_UMIN_I32_POSTRA : Atomic2OpsPostRA; ++def ATOMIC_LOAD_UMAX_I8_POSTRA : Atomic2OpsSubwordPostRA; ++def ATOMIC_LOAD_UMAX_I16_POSTRA : Atomic2OpsSubwordPostRA; ++def ATOMIC_LOAD_UMAX_I32_POSTRA : Atomic2OpsPostRA; ++ + /// Pseudo instructions for loading and storing accumulator registers. + let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { + def LOAD_ACC64 : Load<"", ACC64>; +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsScheduleGeneric.td +=================================================================== +--- llvm-toolchain-9-9.0.1~+rc3.orig/llvm/lib/Target/Mips/MipsScheduleGeneric.td ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsScheduleGeneric.td +@@ -1610,5 +1610,6 @@ def : InstRW<[GenericWriteAtomic], + def : InstRW<[GenericWriteAtomic], + (instregex "^ATOMIC_CMP_SWAP_I(8|16|32|64)_POSTRA$")>; + def : InstRW<[GenericWriteAtomic], +- (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND)_I(8|16|32|64)_POSTRA$")>; ++ (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)" ++ "_I(8|16|32|64)_POSTRA$")>; + } +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsScheduleP5600.td +=================================================================== +--- llvm-toolchain-9-9.0.1~+rc3.orig/llvm/lib/Target/Mips/MipsScheduleP5600.td ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/lib/Target/Mips/MipsScheduleP5600.td +@@ -631,5 +631,6 @@ def : InstRW<[P5600WriteAtomic], + def : InstRW<[P5600WriteAtomic], + (instregex "^ATOMIC_CMP_SWAP_I(8|16|32|64)_POSTRA$")>; + def : InstRW<[P5600WriteAtomic], +- (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND)_I(8|16|32|64)_POSTRA$")>; ++ (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)" ++ "_I(8|16|32|64)_POSTRA$")>; + } +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/test/CodeGen/Mips/atomic-min-max-64.ll +=================================================================== +--- /dev/null ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/test/CodeGen/Mips/atomic-min-max-64.ll +@@ -0,0 +1,158 @@ ++; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ++; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS ++; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS ++; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 ++; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 ++ ++define i64 @test_max(i64* nocapture %ptr, i64 signext %val) { ++; MIPS-LABEL: test_max: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: .LBB0_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: lld $2, 0($4) ++; MIPS-NEXT: slt $3, $2, $5 ++; MIPS-NEXT: move $1, $2 ++; MIPS-NEXT: movn $1, $5, $3 ++; MIPS-NEXT: scd $1, 0($4) ++; MIPS-NEXT: beqz $1, .LBB0_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_max: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: .LBB0_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: lld $2, 0($4) ++; MIPSR6-NEXT: slt $3, $2, $5 ++; MIPSR6-NEXT: seleqz $1, $2, $3 ++; MIPSR6-NEXT: selnez $3, $5, $3 ++; MIPSR6-NEXT: or $1, $1, $3 ++; MIPSR6-NEXT: scd $1, 0($4) ++; MIPSR6-NEXT: beqzc $1, .LBB0_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw max i64* %ptr, i64 %val seq_cst ++ ret i64 %0 ++} ++ ++define i64 @test_min(i64* nocapture %ptr, i64 signext %val) { ++; MIPS-LABEL: test_min: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: .LBB1_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: lld $2, 0($4) ++; MIPS-NEXT: slt $3, $2, $5 ++; MIPS-NEXT: move $1, $2 ++; MIPS-NEXT: movz $1, $5, $3 ++; MIPS-NEXT: scd $1, 0($4) ++; MIPS-NEXT: beqz $1, .LBB1_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_min: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: .LBB1_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: lld $2, 0($4) ++; MIPSR6-NEXT: slt $3, $2, $5 ++; MIPSR6-NEXT: selnez $1, $2, $3 ++; MIPSR6-NEXT: seleqz $3, $5, $3 ++; MIPSR6-NEXT: or $1, $1, $3 ++; MIPSR6-NEXT: scd $1, 0($4) ++; MIPSR6-NEXT: beqzc $1, .LBB1_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw min i64* %ptr, i64 %val seq_cst ++ ret i64 %0 ++} ++ ++define i64 @test_umax(i64* nocapture %ptr, i64 zeroext %val) { ++; MIPS-LABEL: test_umax: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: .LBB2_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: lld $2, 0($4) ++; MIPS-NEXT: sltu $3, $2, $5 ++; MIPS-NEXT: move $1, $2 ++; MIPS-NEXT: movn $1, $5, $3 ++; MIPS-NEXT: scd $1, 0($4) ++; MIPS-NEXT: beqz $1, .LBB2_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_umax: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: .LBB2_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: lld $2, 0($4) ++; MIPSR6-NEXT: sltu $3, $2, $5 ++; MIPSR6-NEXT: seleqz $1, $2, $3 ++; MIPSR6-NEXT: selnez $3, $5, $3 ++; MIPSR6-NEXT: or $1, $1, $3 ++; MIPSR6-NEXT: scd $1, 0($4) ++; MIPSR6-NEXT: beqzc $1, .LBB2_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw umax i64* %ptr, i64 %val seq_cst ++ ret i64 %0 ++} ++ ++define i64 @test_umin(i64* nocapture %ptr, i64 zeroext %val) { ++; MIPS-LABEL: test_umin: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: .LBB3_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: lld $2, 0($4) ++; MIPS-NEXT: sltu $3, $2, $5 ++; MIPS-NEXT: move $1, $2 ++; MIPS-NEXT: movz $1, $5, $3 ++; MIPS-NEXT: scd $1, 0($4) ++; MIPS-NEXT: beqz $1, .LBB3_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_umin: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: .LBB3_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: lld $2, 0($4) ++; MIPSR6-NEXT: sltu $3, $2, $5 ++; MIPSR6-NEXT: selnez $1, $2, $3 ++; MIPSR6-NEXT: seleqz $3, $5, $3 ++; MIPSR6-NEXT: or $1, $1, $3 ++; MIPSR6-NEXT: scd $1, 0($4) ++; MIPSR6-NEXT: beqzc $1, .LBB3_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw umin i64* %ptr, i64 %val seq_cst ++ ret i64 %0 ++} ++ +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/test/CodeGen/Mips/atomic-min-max.ll +=================================================================== +--- /dev/null ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/test/CodeGen/Mips/atomic-min-max.ll +@@ -0,0 +1,4674 @@ ++; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ++; RUN: llc -march=mips -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS ++; RUN: llc -march=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 ++; RUN: llc -march=mips -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM ++; RUN: llc -march=mips -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6 ++; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL ++; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6 ++; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL ++; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6 ++; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64 ++; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6 ++; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL ++; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6 ++ ++define i32 @test_max_32(i32* nocapture %ptr, i32 signext %val) { ++; MIPS-LABEL: test_max_32: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: $BB0_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $2, 0($4) ++; MIPS-NEXT: slt $3, $2, $5 ++; MIPS-NEXT: move $1, $2 ++; MIPS-NEXT: movn $1, $5, $3 ++; MIPS-NEXT: sc $1, 0($4) ++; MIPS-NEXT: beqz $1, $BB0_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_max_32: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: $BB0_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $2, 0($4) ++; MIPSR6-NEXT: slt $3, $2, $5 ++; MIPSR6-NEXT: seleqz $1, $2, $3 ++; MIPSR6-NEXT: selnez $3, $5, $3 ++; MIPSR6-NEXT: or $1, $1, $3 ++; MIPSR6-NEXT: sc $1, 0($4) ++; MIPSR6-NEXT: beqzc $1, $BB0_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_max_32: ++; MM: # %bb.0: # %entry ++; MM-NEXT: sync ++; MM-NEXT: $BB0_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $2, 0($4) ++; MM-NEXT: slt $3, $2, $5 ++; MM-NEXT: or $1, $2, $zero ++; MM-NEXT: movn $1, $5, $3 ++; MM-NEXT: sc $1, 0($4) ++; MM-NEXT: beqzc $1, $BB0_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: sync ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_max_32: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: $BB0_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $2, 0($4) ++; MMR6-NEXT: slt $3, $2, $5 ++; MMR6-NEXT: seleqz $1, $2, $3 ++; MMR6-NEXT: selnez $3, $5, $3 ++; MMR6-NEXT: or $1, $1, $3 ++; MMR6-NEXT: sc $1, 0($4) ++; MMR6-NEXT: beqc $1, $zero, $BB0_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_max_32: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: $BB0_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $2, 0($4) ++; MIPSEL-NEXT: slt $3, $2, $5 ++; MIPSEL-NEXT: move $1, $2 ++; MIPSEL-NEXT: movn $1, $5, $3 ++; MIPSEL-NEXT: sc $1, 0($4) ++; MIPSEL-NEXT: beqz $1, $BB0_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_max_32: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: $BB0_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $2, 0($4) ++; MIPSELR6-NEXT: slt $3, $2, $5 ++; MIPSELR6-NEXT: seleqz $1, $2, $3 ++; MIPSELR6-NEXT: selnez $3, $5, $3 ++; MIPSELR6-NEXT: or $1, $1, $3 ++; MIPSELR6-NEXT: sc $1, 0($4) ++; MIPSELR6-NEXT: beqzc $1, $BB0_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_max_32: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: $BB0_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $2, 0($4) ++; MMEL-NEXT: slt $3, $2, $5 ++; MMEL-NEXT: or $1, $2, $zero ++; MMEL-NEXT: movn $1, $5, $3 ++; MMEL-NEXT: sc $1, 0($4) ++; MMEL-NEXT: beqzc $1, $BB0_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_max_32: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: $BB0_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $2, 0($4) ++; MMELR6-NEXT: slt $3, $2, $5 ++; MMELR6-NEXT: seleqz $1, $2, $3 ++; MMELR6-NEXT: selnez $3, $5, $3 ++; MMELR6-NEXT: or $1, $1, $3 ++; MMELR6-NEXT: sc $1, 0($4) ++; MMELR6-NEXT: beqc $1, $zero, $BB0_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_max_32: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: .LBB0_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $2, 0($4) ++; MIPS64-NEXT: slt $3, $2, $5 ++; MIPS64-NEXT: move $1, $2 ++; MIPS64-NEXT: movn $1, $5, $3 ++; MIPS64-NEXT: sc $1, 0($4) ++; MIPS64-NEXT: beqz $1, .LBB0_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_max_32: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: .LBB0_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $2, 0($4) ++; MIPS64R6-NEXT: slt $3, $2, $5 ++; MIPS64R6-NEXT: seleqz $1, $2, $3 ++; MIPS64R6-NEXT: selnez $3, $5, $3 ++; MIPS64R6-NEXT: or $1, $1, $3 ++; MIPS64R6-NEXT: sc $1, 0($4) ++; MIPS64R6-NEXT: beqzc $1, .LBB0_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_max_32: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: .LBB0_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $2, 0($4) ++; MIPS64EL-NEXT: slt $3, $2, $5 ++; MIPS64EL-NEXT: move $1, $2 ++; MIPS64EL-NEXT: movn $1, $5, $3 ++; MIPS64EL-NEXT: sc $1, 0($4) ++; MIPS64EL-NEXT: beqz $1, .LBB0_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_max_32: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: .LBB0_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $2, 0($4) ++; MIPS64ELR6-NEXT: slt $3, $2, $5 ++; MIPS64ELR6-NEXT: seleqz $1, $2, $3 ++; MIPS64ELR6-NEXT: selnez $3, $5, $3 ++; MIPS64ELR6-NEXT: or $1, $1, $3 ++; MIPS64ELR6-NEXT: sc $1, 0($4) ++; MIPS64ELR6-NEXT: beqzc $1, .LBB0_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw max i32* %ptr, i32 %val seq_cst ++ ret i32 %0 ++} ++ ++define i32 @test_min_32(i32* nocapture %ptr, i32 signext %val) { ++; MIPS-LABEL: test_min_32: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: $BB1_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $2, 0($4) ++; MIPS-NEXT: slt $3, $2, $5 ++; MIPS-NEXT: move $1, $2 ++; MIPS-NEXT: movz $1, $5, $3 ++; MIPS-NEXT: sc $1, 0($4) ++; MIPS-NEXT: beqz $1, $BB1_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_min_32: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: $BB1_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $2, 0($4) ++; MIPSR6-NEXT: slt $3, $2, $5 ++; MIPSR6-NEXT: selnez $1, $2, $3 ++; MIPSR6-NEXT: seleqz $3, $5, $3 ++; MIPSR6-NEXT: or $1, $1, $3 ++; MIPSR6-NEXT: sc $1, 0($4) ++; MIPSR6-NEXT: beqzc $1, $BB1_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_min_32: ++; MM: # %bb.0: # %entry ++; MM-NEXT: sync ++; MM-NEXT: $BB1_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $2, 0($4) ++; MM-NEXT: slt $3, $2, $5 ++; MM-NEXT: or $1, $2, $zero ++; MM-NEXT: movz $1, $5, $3 ++; MM-NEXT: sc $1, 0($4) ++; MM-NEXT: beqzc $1, $BB1_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: sync ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_min_32: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: $BB1_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $2, 0($4) ++; MMR6-NEXT: slt $3, $2, $5 ++; MMR6-NEXT: selnez $1, $2, $3 ++; MMR6-NEXT: seleqz $3, $5, $3 ++; MMR6-NEXT: or $1, $1, $3 ++; MMR6-NEXT: sc $1, 0($4) ++; MMR6-NEXT: beqc $1, $zero, $BB1_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_min_32: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: $BB1_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $2, 0($4) ++; MIPSEL-NEXT: slt $3, $2, $5 ++; MIPSEL-NEXT: move $1, $2 ++; MIPSEL-NEXT: movz $1, $5, $3 ++; MIPSEL-NEXT: sc $1, 0($4) ++; MIPSEL-NEXT: beqz $1, $BB1_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_min_32: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: $BB1_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $2, 0($4) ++; MIPSELR6-NEXT: slt $3, $2, $5 ++; MIPSELR6-NEXT: selnez $1, $2, $3 ++; MIPSELR6-NEXT: seleqz $3, $5, $3 ++; MIPSELR6-NEXT: or $1, $1, $3 ++; MIPSELR6-NEXT: sc $1, 0($4) ++; MIPSELR6-NEXT: beqzc $1, $BB1_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_min_32: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: $BB1_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $2, 0($4) ++; MMEL-NEXT: slt $3, $2, $5 ++; MMEL-NEXT: or $1, $2, $zero ++; MMEL-NEXT: movz $1, $5, $3 ++; MMEL-NEXT: sc $1, 0($4) ++; MMEL-NEXT: beqzc $1, $BB1_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_min_32: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: $BB1_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $2, 0($4) ++; MMELR6-NEXT: slt $3, $2, $5 ++; MMELR6-NEXT: selnez $1, $2, $3 ++; MMELR6-NEXT: seleqz $3, $5, $3 ++; MMELR6-NEXT: or $1, $1, $3 ++; MMELR6-NEXT: sc $1, 0($4) ++; MMELR6-NEXT: beqc $1, $zero, $BB1_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_min_32: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: .LBB1_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $2, 0($4) ++; MIPS64-NEXT: slt $3, $2, $5 ++; MIPS64-NEXT: move $1, $2 ++; MIPS64-NEXT: movz $1, $5, $3 ++; MIPS64-NEXT: sc $1, 0($4) ++; MIPS64-NEXT: beqz $1, .LBB1_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_min_32: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: .LBB1_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $2, 0($4) ++; MIPS64R6-NEXT: slt $3, $2, $5 ++; MIPS64R6-NEXT: selnez $1, $2, $3 ++; MIPS64R6-NEXT: seleqz $3, $5, $3 ++; MIPS64R6-NEXT: or $1, $1, $3 ++; MIPS64R6-NEXT: sc $1, 0($4) ++; MIPS64R6-NEXT: beqzc $1, .LBB1_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_min_32: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: .LBB1_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $2, 0($4) ++; MIPS64EL-NEXT: slt $3, $2, $5 ++; MIPS64EL-NEXT: move $1, $2 ++; MIPS64EL-NEXT: movz $1, $5, $3 ++; MIPS64EL-NEXT: sc $1, 0($4) ++; MIPS64EL-NEXT: beqz $1, .LBB1_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_min_32: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: .LBB1_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $2, 0($4) ++; MIPS64ELR6-NEXT: slt $3, $2, $5 ++; MIPS64ELR6-NEXT: selnez $1, $2, $3 ++; MIPS64ELR6-NEXT: seleqz $3, $5, $3 ++; MIPS64ELR6-NEXT: or $1, $1, $3 ++; MIPS64ELR6-NEXT: sc $1, 0($4) ++; MIPS64ELR6-NEXT: beqzc $1, .LBB1_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw min i32* %ptr, i32 %val seq_cst ++ ret i32 %0 ++} ++ ++define i32 @test_umax_32(i32* nocapture %ptr, i32 signext %val) { ++; MIPS-LABEL: test_umax_32: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: $BB2_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $2, 0($4) ++; MIPS-NEXT: sltu $3, $2, $5 ++; MIPS-NEXT: move $1, $2 ++; MIPS-NEXT: movn $1, $5, $3 ++; MIPS-NEXT: sc $1, 0($4) ++; MIPS-NEXT: beqz $1, $BB2_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_umax_32: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: $BB2_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $2, 0($4) ++; MIPSR6-NEXT: sltu $3, $2, $5 ++; MIPSR6-NEXT: seleqz $1, $2, $3 ++; MIPSR6-NEXT: selnez $3, $5, $3 ++; MIPSR6-NEXT: or $1, $1, $3 ++; MIPSR6-NEXT: sc $1, 0($4) ++; MIPSR6-NEXT: beqzc $1, $BB2_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_umax_32: ++; MM: # %bb.0: # %entry ++; MM-NEXT: sync ++; MM-NEXT: $BB2_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $2, 0($4) ++; MM-NEXT: sltu $3, $2, $5 ++; MM-NEXT: or $1, $2, $zero ++; MM-NEXT: movn $1, $5, $3 ++; MM-NEXT: sc $1, 0($4) ++; MM-NEXT: beqzc $1, $BB2_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: sync ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_umax_32: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: $BB2_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $2, 0($4) ++; MMR6-NEXT: sltu $3, $2, $5 ++; MMR6-NEXT: seleqz $1, $2, $3 ++; MMR6-NEXT: selnez $3, $5, $3 ++; MMR6-NEXT: or $1, $1, $3 ++; MMR6-NEXT: sc $1, 0($4) ++; MMR6-NEXT: beqc $1, $zero, $BB2_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_umax_32: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: $BB2_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $2, 0($4) ++; MIPSEL-NEXT: sltu $3, $2, $5 ++; MIPSEL-NEXT: move $1, $2 ++; MIPSEL-NEXT: movn $1, $5, $3 ++; MIPSEL-NEXT: sc $1, 0($4) ++; MIPSEL-NEXT: beqz $1, $BB2_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_umax_32: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: $BB2_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $2, 0($4) ++; MIPSELR6-NEXT: sltu $3, $2, $5 ++; MIPSELR6-NEXT: seleqz $1, $2, $3 ++; MIPSELR6-NEXT: selnez $3, $5, $3 ++; MIPSELR6-NEXT: or $1, $1, $3 ++; MIPSELR6-NEXT: sc $1, 0($4) ++; MIPSELR6-NEXT: beqzc $1, $BB2_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_umax_32: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: $BB2_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $2, 0($4) ++; MMEL-NEXT: sltu $3, $2, $5 ++; MMEL-NEXT: or $1, $2, $zero ++; MMEL-NEXT: movn $1, $5, $3 ++; MMEL-NEXT: sc $1, 0($4) ++; MMEL-NEXT: beqzc $1, $BB2_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_umax_32: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: $BB2_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $2, 0($4) ++; MMELR6-NEXT: sltu $3, $2, $5 ++; MMELR6-NEXT: seleqz $1, $2, $3 ++; MMELR6-NEXT: selnez $3, $5, $3 ++; MMELR6-NEXT: or $1, $1, $3 ++; MMELR6-NEXT: sc $1, 0($4) ++; MMELR6-NEXT: beqc $1, $zero, $BB2_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_umax_32: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: .LBB2_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $2, 0($4) ++; MIPS64-NEXT: sltu $3, $2, $5 ++; MIPS64-NEXT: move $1, $2 ++; MIPS64-NEXT: movn $1, $5, $3 ++; MIPS64-NEXT: sc $1, 0($4) ++; MIPS64-NEXT: beqz $1, .LBB2_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_umax_32: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: .LBB2_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $2, 0($4) ++; MIPS64R6-NEXT: sltu $3, $2, $5 ++; MIPS64R6-NEXT: seleqz $1, $2, $3 ++; MIPS64R6-NEXT: selnez $3, $5, $3 ++; MIPS64R6-NEXT: or $1, $1, $3 ++; MIPS64R6-NEXT: sc $1, 0($4) ++; MIPS64R6-NEXT: beqzc $1, .LBB2_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_umax_32: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: .LBB2_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $2, 0($4) ++; MIPS64EL-NEXT: sltu $3, $2, $5 ++; MIPS64EL-NEXT: move $1, $2 ++; MIPS64EL-NEXT: movn $1, $5, $3 ++; MIPS64EL-NEXT: sc $1, 0($4) ++; MIPS64EL-NEXT: beqz $1, .LBB2_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_umax_32: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: .LBB2_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $2, 0($4) ++; MIPS64ELR6-NEXT: sltu $3, $2, $5 ++; MIPS64ELR6-NEXT: seleqz $1, $2, $3 ++; MIPS64ELR6-NEXT: selnez $3, $5, $3 ++; MIPS64ELR6-NEXT: or $1, $1, $3 ++; MIPS64ELR6-NEXT: sc $1, 0($4) ++; MIPS64ELR6-NEXT: beqzc $1, .LBB2_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw umax i32* %ptr, i32 %val seq_cst ++ ret i32 %0 ++} ++ ++define i32 @test_umin_32(i32* nocapture %ptr, i32 signext %val) { ++; MIPS-LABEL: test_umin_32: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: $BB3_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $2, 0($4) ++; MIPS-NEXT: sltu $3, $2, $5 ++; MIPS-NEXT: move $1, $2 ++; MIPS-NEXT: movz $1, $5, $3 ++; MIPS-NEXT: sc $1, 0($4) ++; MIPS-NEXT: beqz $1, $BB3_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_umin_32: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: $BB3_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $2, 0($4) ++; MIPSR6-NEXT: sltu $3, $2, $5 ++; MIPSR6-NEXT: selnez $1, $2, $3 ++; MIPSR6-NEXT: seleqz $3, $5, $3 ++; MIPSR6-NEXT: or $1, $1, $3 ++; MIPSR6-NEXT: sc $1, 0($4) ++; MIPSR6-NEXT: beqzc $1, $BB3_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_umin_32: ++; MM: # %bb.0: # %entry ++; MM-NEXT: sync ++; MM-NEXT: $BB3_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $2, 0($4) ++; MM-NEXT: sltu $3, $2, $5 ++; MM-NEXT: or $1, $2, $zero ++; MM-NEXT: movz $1, $5, $3 ++; MM-NEXT: sc $1, 0($4) ++; MM-NEXT: beqzc $1, $BB3_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: sync ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_umin_32: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: $BB3_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $2, 0($4) ++; MMR6-NEXT: sltu $3, $2, $5 ++; MMR6-NEXT: selnez $1, $2, $3 ++; MMR6-NEXT: seleqz $3, $5, $3 ++; MMR6-NEXT: or $1, $1, $3 ++; MMR6-NEXT: sc $1, 0($4) ++; MMR6-NEXT: beqc $1, $zero, $BB3_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_umin_32: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: $BB3_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $2, 0($4) ++; MIPSEL-NEXT: sltu $3, $2, $5 ++; MIPSEL-NEXT: move $1, $2 ++; MIPSEL-NEXT: movz $1, $5, $3 ++; MIPSEL-NEXT: sc $1, 0($4) ++; MIPSEL-NEXT: beqz $1, $BB3_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_umin_32: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: $BB3_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $2, 0($4) ++; MIPSELR6-NEXT: sltu $3, $2, $5 ++; MIPSELR6-NEXT: selnez $1, $2, $3 ++; MIPSELR6-NEXT: seleqz $3, $5, $3 ++; MIPSELR6-NEXT: or $1, $1, $3 ++; MIPSELR6-NEXT: sc $1, 0($4) ++; MIPSELR6-NEXT: beqzc $1, $BB3_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_umin_32: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: $BB3_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $2, 0($4) ++; MMEL-NEXT: sltu $3, $2, $5 ++; MMEL-NEXT: or $1, $2, $zero ++; MMEL-NEXT: movz $1, $5, $3 ++; MMEL-NEXT: sc $1, 0($4) ++; MMEL-NEXT: beqzc $1, $BB3_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_umin_32: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: $BB3_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $2, 0($4) ++; MMELR6-NEXT: sltu $3, $2, $5 ++; MMELR6-NEXT: selnez $1, $2, $3 ++; MMELR6-NEXT: seleqz $3, $5, $3 ++; MMELR6-NEXT: or $1, $1, $3 ++; MMELR6-NEXT: sc $1, 0($4) ++; MMELR6-NEXT: beqc $1, $zero, $BB3_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_umin_32: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: .LBB3_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $2, 0($4) ++; MIPS64-NEXT: sltu $3, $2, $5 ++; MIPS64-NEXT: move $1, $2 ++; MIPS64-NEXT: movz $1, $5, $3 ++; MIPS64-NEXT: sc $1, 0($4) ++; MIPS64-NEXT: beqz $1, .LBB3_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_umin_32: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: .LBB3_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $2, 0($4) ++; MIPS64R6-NEXT: sltu $3, $2, $5 ++; MIPS64R6-NEXT: selnez $1, $2, $3 ++; MIPS64R6-NEXT: seleqz $3, $5, $3 ++; MIPS64R6-NEXT: or $1, $1, $3 ++; MIPS64R6-NEXT: sc $1, 0($4) ++; MIPS64R6-NEXT: beqzc $1, .LBB3_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_umin_32: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: .LBB3_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $2, 0($4) ++; MIPS64EL-NEXT: sltu $3, $2, $5 ++; MIPS64EL-NEXT: move $1, $2 ++; MIPS64EL-NEXT: movz $1, $5, $3 ++; MIPS64EL-NEXT: sc $1, 0($4) ++; MIPS64EL-NEXT: beqz $1, .LBB3_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_umin_32: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: .LBB3_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $2, 0($4) ++; MIPS64ELR6-NEXT: sltu $3, $2, $5 ++; MIPS64ELR6-NEXT: selnez $1, $2, $3 ++; MIPS64ELR6-NEXT: seleqz $3, $5, $3 ++; MIPS64ELR6-NEXT: or $1, $1, $3 ++; MIPS64ELR6-NEXT: sc $1, 0($4) ++; MIPS64ELR6-NEXT: beqzc $1, .LBB3_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw umin i32* %ptr, i32 %val seq_cst ++ ret i32 %0 ++} ++ ++define i16 @test_max_16(i16* nocapture %ptr, i16 signext %val) { ++; MIPS-LABEL: test_max_16: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: addiu $sp, $sp, -8 ++; MIPS-NEXT: .cfi_def_cfa_offset 8 ++; MIPS-NEXT: move $1, $5 ++; MIPS-NEXT: sync ++; MIPS-NEXT: addiu $2, $zero, -4 ++; MIPS-NEXT: and $2, $4, $2 ++; MIPS-NEXT: andi $3, $4, 3 ++; MIPS-NEXT: xori $3, $3, 2 ++; MIPS-NEXT: sll $3, $3, 3 ++; MIPS-NEXT: ori $4, $zero, 65535 ++; MIPS-NEXT: sllv $4, $4, $3 ++; MIPS-NEXT: nor $6, $zero, $4 ++; MIPS-NEXT: sllv $5, $5, $3 ++; MIPS-NEXT: $BB4_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $8, 0($2) ++; MIPS-NEXT: slt $11, $8, $5 ++; MIPS-NEXT: move $9, $8 ++; MIPS-NEXT: movn $9, $5, $11 ++; MIPS-NEXT: and $9, $9, $4 ++; MIPS-NEXT: and $10, $8, $6 ++; MIPS-NEXT: or $10, $10, $9 ++; MIPS-NEXT: sc $10, 0($2) ++; MIPS-NEXT: beqz $10, $BB4_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: and $7, $8, $4 ++; MIPS-NEXT: srlv $7, $7, $3 ++; MIPS-NEXT: seh $7, $7 ++; MIPS-NEXT: # %bb.3: # %entry ++; MIPS-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPS-NEXT: # %bb.4: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPS-NEXT: addiu $sp, $sp, 8 ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_max_16: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: addiu $sp, $sp, -8 ++; MIPSR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSR6-NEXT: move $1, $5 ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: addiu $2, $zero, -4 ++; MIPSR6-NEXT: and $2, $4, $2 ++; MIPSR6-NEXT: andi $3, $4, 3 ++; MIPSR6-NEXT: xori $3, $3, 2 ++; MIPSR6-NEXT: sll $3, $3, 3 ++; MIPSR6-NEXT: ori $4, $zero, 65535 ++; MIPSR6-NEXT: sllv $4, $4, $3 ++; MIPSR6-NEXT: nor $6, $zero, $4 ++; MIPSR6-NEXT: sllv $5, $5, $3 ++; MIPSR6-NEXT: $BB4_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $8, 0($2) ++; MIPSR6-NEXT: slt $11, $8, $5 ++; MIPSR6-NEXT: seleqz $9, $8, $11 ++; MIPSR6-NEXT: selnez $11, $5, $11 ++; MIPSR6-NEXT: or $9, $9, $11 ++; MIPSR6-NEXT: and $9, $9, $4 ++; MIPSR6-NEXT: and $10, $8, $6 ++; MIPSR6-NEXT: or $10, $10, $9 ++; MIPSR6-NEXT: sc $10, 0($2) ++; MIPSR6-NEXT: beqzc $10, $BB4_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: and $7, $8, $4 ++; MIPSR6-NEXT: srlv $7, $7, $3 ++; MIPSR6-NEXT: seh $7, $7 ++; MIPSR6-NEXT: # %bb.3: # %entry ++; MIPSR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSR6-NEXT: # %bb.4: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSR6-NEXT: addiu $sp, $sp, 8 ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_max_16: ++; MM: # %bb.0: # %entry ++; MM-NEXT: addiu $sp, $sp, -8 ++; MM-NEXT: .cfi_def_cfa_offset 8 ++; MM-NEXT: move $1, $5 ++; MM-NEXT: sync ++; MM-NEXT: addiu $2, $zero, -4 ++; MM-NEXT: and $2, $4, $2 ++; MM-NEXT: andi $3, $4, 3 ++; MM-NEXT: xori $3, $3, 2 ++; MM-NEXT: sll $3, $3, 3 ++; MM-NEXT: ori $4, $zero, 65535 ++; MM-NEXT: sllv $4, $4, $3 ++; MM-NEXT: nor $6, $zero, $4 ++; MM-NEXT: sllv $5, $5, $3 ++; MM-NEXT: $BB4_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $8, 0($2) ++; MM-NEXT: slt $11, $8, $5 ++; MM-NEXT: or $9, $8, $zero ++; MM-NEXT: movn $9, $5, $11 ++; MM-NEXT: and $9, $9, $4 ++; MM-NEXT: and $10, $8, $6 ++; MM-NEXT: or $10, $10, $9 ++; MM-NEXT: sc $10, 0($2) ++; MM-NEXT: beqzc $10, $BB4_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: and $7, $8, $4 ++; MM-NEXT: srlv $7, $7, $3 ++; MM-NEXT: seh $7, $7 ++; MM-NEXT: # %bb.3: # %entry ++; MM-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MM-NEXT: # %bb.4: # %entry ++; MM-NEXT: sync ++; MM-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MM-NEXT: addiusp 8 ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_max_16: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: addiu $sp, $sp, -8 ++; MMR6-NEXT: .cfi_def_cfa_offset 8 ++; MMR6-NEXT: move $1, $5 ++; MMR6-NEXT: sync ++; MMR6-NEXT: addiu $2, $zero, -4 ++; MMR6-NEXT: and $2, $4, $2 ++; MMR6-NEXT: andi $3, $4, 3 ++; MMR6-NEXT: xori $3, $3, 2 ++; MMR6-NEXT: sll $3, $3, 3 ++; MMR6-NEXT: ori $4, $zero, 65535 ++; MMR6-NEXT: sllv $4, $4, $3 ++; MMR6-NEXT: nor $6, $zero, $4 ++; MMR6-NEXT: sllv $5, $5, $3 ++; MMR6-NEXT: $BB4_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $8, 0($2) ++; MMR6-NEXT: slt $11, $8, $5 ++; MMR6-NEXT: seleqz $9, $8, $11 ++; MMR6-NEXT: selnez $11, $5, $11 ++; MMR6-NEXT: or $9, $9, $11 ++; MMR6-NEXT: and $9, $9, $4 ++; MMR6-NEXT: and $10, $8, $6 ++; MMR6-NEXT: or $10, $10, $9 ++; MMR6-NEXT: sc $10, 0($2) ++; MMR6-NEXT: beqc $10, $zero, $BB4_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: and $7, $8, $4 ++; MMR6-NEXT: srlv $7, $7, $3 ++; MMR6-NEXT: seh $7, $7 ++; MMR6-NEXT: # %bb.3: # %entry ++; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMR6-NEXT: # %bb.4: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMR6-NEXT: addiu $sp, $sp, 8 ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_max_16: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: addiu $sp, $sp, -8 ++; MIPSEL-NEXT: .cfi_def_cfa_offset 8 ++; MIPSEL-NEXT: move $1, $5 ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: addiu $2, $zero, -4 ++; MIPSEL-NEXT: and $2, $4, $2 ++; MIPSEL-NEXT: andi $3, $4, 3 ++; MIPSEL-NEXT: sll $3, $3, 3 ++; MIPSEL-NEXT: ori $4, $zero, 65535 ++; MIPSEL-NEXT: sllv $4, $4, $3 ++; MIPSEL-NEXT: nor $6, $zero, $4 ++; MIPSEL-NEXT: sllv $5, $5, $3 ++; MIPSEL-NEXT: $BB4_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $8, 0($2) ++; MIPSEL-NEXT: and $8, $8, $4 ++; MIPSEL-NEXT: and $5, $5, $4 ++; MIPSEL-NEXT: slt $11, $8, $5 ++; MIPSEL-NEXT: move $9, $8 ++; MIPSEL-NEXT: movn $9, $5, $11 ++; MIPSEL-NEXT: and $9, $9, $4 ++; MIPSEL-NEXT: and $10, $8, $6 ++; MIPSEL-NEXT: or $10, $10, $9 ++; MIPSEL-NEXT: sc $10, 0($2) ++; MIPSEL-NEXT: beqz $10, $BB4_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: and $7, $8, $4 ++; MIPSEL-NEXT: srlv $7, $7, $3 ++; MIPSEL-NEXT: seh $7, $7 ++; MIPSEL-NEXT: # %bb.3: # %entry ++; MIPSEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSEL-NEXT: # %bb.4: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSEL-NEXT: addiu $sp, $sp, 8 ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_max_16: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: addiu $sp, $sp, -8 ++; MIPSELR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSELR6-NEXT: move $1, $5 ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: addiu $2, $zero, -4 ++; MIPSELR6-NEXT: and $2, $4, $2 ++; MIPSELR6-NEXT: andi $3, $4, 3 ++; MIPSELR6-NEXT: sll $3, $3, 3 ++; MIPSELR6-NEXT: ori $4, $zero, 65535 ++; MIPSELR6-NEXT: sllv $4, $4, $3 ++; MIPSELR6-NEXT: nor $6, $zero, $4 ++; MIPSELR6-NEXT: sllv $5, $5, $3 ++; MIPSELR6-NEXT: $BB4_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $8, 0($2) ++; MIPSELR6-NEXT: and $8, $8, $4 ++; MIPSELR6-NEXT: and $5, $5, $4 ++; MIPSELR6-NEXT: slt $11, $8, $5 ++; MIPSELR6-NEXT: seleqz $9, $8, $11 ++; MIPSELR6-NEXT: selnez $11, $5, $11 ++; MIPSELR6-NEXT: or $9, $9, $11 ++; MIPSELR6-NEXT: and $9, $9, $4 ++; MIPSELR6-NEXT: and $10, $8, $6 ++; MIPSELR6-NEXT: or $10, $10, $9 ++; MIPSELR6-NEXT: sc $10, 0($2) ++; MIPSELR6-NEXT: beqzc $10, $BB4_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: and $7, $8, $4 ++; MIPSELR6-NEXT: srlv $7, $7, $3 ++; MIPSELR6-NEXT: seh $7, $7 ++; MIPSELR6-NEXT: # %bb.3: # %entry ++; MIPSELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSELR6-NEXT: # %bb.4: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSELR6-NEXT: addiu $sp, $sp, 8 ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_max_16: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: addiu $sp, $sp, -8 ++; MMEL-NEXT: .cfi_def_cfa_offset 8 ++; MMEL-NEXT: move $1, $5 ++; MMEL-NEXT: sync ++; MMEL-NEXT: addiu $2, $zero, -4 ++; MMEL-NEXT: and $2, $4, $2 ++; MMEL-NEXT: andi $3, $4, 3 ++; MMEL-NEXT: sll $3, $3, 3 ++; MMEL-NEXT: ori $4, $zero, 65535 ++; MMEL-NEXT: sllv $4, $4, $3 ++; MMEL-NEXT: nor $6, $zero, $4 ++; MMEL-NEXT: sllv $5, $5, $3 ++; MMEL-NEXT: $BB4_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $8, 0($2) ++; MMEL-NEXT: and $8, $8, $4 ++; MMEL-NEXT: and $5, $5, $4 ++; MMEL-NEXT: slt $11, $8, $5 ++; MMEL-NEXT: or $9, $8, $zero ++; MMEL-NEXT: movn $9, $5, $11 ++; MMEL-NEXT: and $9, $9, $4 ++; MMEL-NEXT: and $10, $8, $6 ++; MMEL-NEXT: or $10, $10, $9 ++; MMEL-NEXT: sc $10, 0($2) ++; MMEL-NEXT: beqzc $10, $BB4_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: and $7, $8, $4 ++; MMEL-NEXT: srlv $7, $7, $3 ++; MMEL-NEXT: seh $7, $7 ++; MMEL-NEXT: # %bb.3: # %entry ++; MMEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMEL-NEXT: # %bb.4: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMEL-NEXT: addiusp 8 ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_max_16: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: addiu $sp, $sp, -8 ++; MMELR6-NEXT: .cfi_def_cfa_offset 8 ++; MMELR6-NEXT: move $1, $5 ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: addiu $2, $zero, -4 ++; MMELR6-NEXT: and $2, $4, $2 ++; MMELR6-NEXT: andi $3, $4, 3 ++; MMELR6-NEXT: sll $3, $3, 3 ++; MMELR6-NEXT: ori $4, $zero, 65535 ++; MMELR6-NEXT: sllv $4, $4, $3 ++; MMELR6-NEXT: nor $6, $zero, $4 ++; MMELR6-NEXT: sllv $5, $5, $3 ++; MMELR6-NEXT: $BB4_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $8, 0($2) ++; MMELR6-NEXT: and $8, $8, $4 ++; MMELR6-NEXT: and $5, $5, $4 ++; MMELR6-NEXT: slt $11, $8, $5 ++; MMELR6-NEXT: seleqz $9, $8, $11 ++; MMELR6-NEXT: selnez $11, $5, $11 ++; MMELR6-NEXT: or $9, $9, $11 ++; MMELR6-NEXT: and $9, $9, $4 ++; MMELR6-NEXT: and $10, $8, $6 ++; MMELR6-NEXT: or $10, $10, $9 ++; MMELR6-NEXT: sc $10, 0($2) ++; MMELR6-NEXT: beqc $10, $zero, $BB4_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: and $7, $8, $4 ++; MMELR6-NEXT: srlv $7, $7, $3 ++; MMELR6-NEXT: seh $7, $7 ++; MMELR6-NEXT: # %bb.3: # %entry ++; MMELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMELR6-NEXT: # %bb.4: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMELR6-NEXT: addiu $sp, $sp, 8 ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_max_16: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: daddiu $sp, $sp, -16 ++; MIPS64-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: daddiu $1, $zero, -4 ++; MIPS64-NEXT: and $1, $4, $1 ++; MIPS64-NEXT: andi $2, $4, 3 ++; MIPS64-NEXT: xori $2, $2, 2 ++; MIPS64-NEXT: sll $2, $2, 3 ++; MIPS64-NEXT: ori $3, $zero, 65535 ++; MIPS64-NEXT: sllv $3, $3, $2 ++; MIPS64-NEXT: nor $6, $zero, $3 ++; MIPS64-NEXT: sllv $5, $5, $2 ++; MIPS64-NEXT: .LBB4_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $8, 0($1) ++; MIPS64-NEXT: slt $11, $8, $5 ++; MIPS64-NEXT: move $9, $8 ++; MIPS64-NEXT: movn $9, $5, $11 ++; MIPS64-NEXT: and $9, $9, $3 ++; MIPS64-NEXT: and $10, $8, $6 ++; MIPS64-NEXT: or $10, $10, $9 ++; MIPS64-NEXT: sc $10, 0($1) ++; MIPS64-NEXT: beqz $10, .LBB4_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: and $7, $8, $3 ++; MIPS64-NEXT: srlv $7, $7, $2 ++; MIPS64-NEXT: seh $7, $7 ++; MIPS64-NEXT: # %bb.3: # %entry ++; MIPS64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64-NEXT: # %bb.4: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64-NEXT: daddiu $sp, $sp, 16 ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_max_16: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64R6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: daddiu $1, $zero, -4 ++; MIPS64R6-NEXT: and $1, $4, $1 ++; MIPS64R6-NEXT: andi $2, $4, 3 ++; MIPS64R6-NEXT: xori $2, $2, 2 ++; MIPS64R6-NEXT: sll $2, $2, 3 ++; MIPS64R6-NEXT: ori $3, $zero, 65535 ++; MIPS64R6-NEXT: sllv $3, $3, $2 ++; MIPS64R6-NEXT: nor $6, $zero, $3 ++; MIPS64R6-NEXT: sllv $5, $5, $2 ++; MIPS64R6-NEXT: .LBB4_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $8, 0($1) ++; MIPS64R6-NEXT: slt $11, $8, $5 ++; MIPS64R6-NEXT: seleqz $9, $8, $11 ++; MIPS64R6-NEXT: selnez $11, $5, $11 ++; MIPS64R6-NEXT: or $9, $9, $11 ++; MIPS64R6-NEXT: and $9, $9, $3 ++; MIPS64R6-NEXT: and $10, $8, $6 ++; MIPS64R6-NEXT: or $10, $10, $9 ++; MIPS64R6-NEXT: sc $10, 0($1) ++; MIPS64R6-NEXT: beqzc $10, .LBB4_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: and $7, $8, $3 ++; MIPS64R6-NEXT: srlv $7, $7, $2 ++; MIPS64R6-NEXT: seh $7, $7 ++; MIPS64R6-NEXT: # %bb.3: # %entry ++; MIPS64R6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64R6-NEXT: # %bb.4: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64R6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_max_16: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: daddiu $sp, $sp, -16 ++; MIPS64EL-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: daddiu $1, $zero, -4 ++; MIPS64EL-NEXT: and $1, $4, $1 ++; MIPS64EL-NEXT: andi $2, $4, 3 ++; MIPS64EL-NEXT: sll $2, $2, 3 ++; MIPS64EL-NEXT: ori $3, $zero, 65535 ++; MIPS64EL-NEXT: sllv $3, $3, $2 ++; MIPS64EL-NEXT: nor $6, $zero, $3 ++; MIPS64EL-NEXT: sllv $5, $5, $2 ++; MIPS64EL-NEXT: .LBB4_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $8, 0($1) ++; MIPS64EL-NEXT: and $8, $8, $3 ++; MIPS64EL-NEXT: and $5, $5, $3 ++; MIPS64EL-NEXT: slt $11, $8, $5 ++; MIPS64EL-NEXT: move $9, $8 ++; MIPS64EL-NEXT: movn $9, $5, $11 ++; MIPS64EL-NEXT: and $9, $9, $3 ++; MIPS64EL-NEXT: and $10, $8, $6 ++; MIPS64EL-NEXT: or $10, $10, $9 ++; MIPS64EL-NEXT: sc $10, 0($1) ++; MIPS64EL-NEXT: beqz $10, .LBB4_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: and $7, $8, $3 ++; MIPS64EL-NEXT: srlv $7, $7, $2 ++; MIPS64EL-NEXT: seh $7, $7 ++; MIPS64EL-NEXT: # %bb.3: # %entry ++; MIPS64EL-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64EL-NEXT: # %bb.4: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64EL-NEXT: daddiu $sp, $sp, 16 ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_max_16: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64ELR6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: daddiu $1, $zero, -4 ++; MIPS64ELR6-NEXT: and $1, $4, $1 ++; MIPS64ELR6-NEXT: andi $2, $4, 3 ++; MIPS64ELR6-NEXT: sll $2, $2, 3 ++; MIPS64ELR6-NEXT: ori $3, $zero, 65535 ++; MIPS64ELR6-NEXT: sllv $3, $3, $2 ++; MIPS64ELR6-NEXT: nor $6, $zero, $3 ++; MIPS64ELR6-NEXT: sllv $5, $5, $2 ++; MIPS64ELR6-NEXT: .LBB4_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $8, 0($1) ++; MIPS64ELR6-NEXT: and $8, $8, $3 ++; MIPS64ELR6-NEXT: and $5, $5, $3 ++; MIPS64ELR6-NEXT: slt $11, $8, $5 ++; MIPS64ELR6-NEXT: seleqz $9, $8, $11 ++; MIPS64ELR6-NEXT: selnez $11, $5, $11 ++; MIPS64ELR6-NEXT: or $9, $9, $11 ++; MIPS64ELR6-NEXT: and $9, $9, $3 ++; MIPS64ELR6-NEXT: and $10, $8, $6 ++; MIPS64ELR6-NEXT: or $10, $10, $9 ++; MIPS64ELR6-NEXT: sc $10, 0($1) ++; MIPS64ELR6-NEXT: beqzc $10, .LBB4_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: and $7, $8, $3 ++; MIPS64ELR6-NEXT: srlv $7, $7, $2 ++; MIPS64ELR6-NEXT: seh $7, $7 ++; MIPS64ELR6-NEXT: # %bb.3: # %entry ++; MIPS64ELR6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64ELR6-NEXT: # %bb.4: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw max i16* %ptr, i16 %val seq_cst ++ ret i16 %0 ++} ++ ++define i16 @test_min_16(i16* nocapture %ptr, i16 signext %val) { ++; MIPS-LABEL: test_min_16: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: addiu $sp, $sp, -8 ++; MIPS-NEXT: .cfi_def_cfa_offset 8 ++; MIPS-NEXT: move $1, $5 ++; MIPS-NEXT: sync ++; MIPS-NEXT: addiu $2, $zero, -4 ++; MIPS-NEXT: and $2, $4, $2 ++; MIPS-NEXT: andi $3, $4, 3 ++; MIPS-NEXT: xori $3, $3, 2 ++; MIPS-NEXT: sll $3, $3, 3 ++; MIPS-NEXT: ori $4, $zero, 65535 ++; MIPS-NEXT: sllv $4, $4, $3 ++; MIPS-NEXT: nor $6, $zero, $4 ++; MIPS-NEXT: sllv $5, $5, $3 ++; MIPS-NEXT: $BB5_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $8, 0($2) ++; MIPS-NEXT: slt $11, $8, $5 ++; MIPS-NEXT: move $9, $8 ++; MIPS-NEXT: movz $9, $5, $11 ++; MIPS-NEXT: and $9, $9, $4 ++; MIPS-NEXT: and $10, $8, $6 ++; MIPS-NEXT: or $10, $10, $9 ++; MIPS-NEXT: sc $10, 0($2) ++; MIPS-NEXT: beqz $10, $BB5_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: and $7, $8, $4 ++; MIPS-NEXT: srlv $7, $7, $3 ++; MIPS-NEXT: seh $7, $7 ++; MIPS-NEXT: # %bb.3: # %entry ++; MIPS-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPS-NEXT: # %bb.4: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPS-NEXT: addiu $sp, $sp, 8 ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_min_16: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: addiu $sp, $sp, -8 ++; MIPSR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSR6-NEXT: move $1, $5 ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: addiu $2, $zero, -4 ++; MIPSR6-NEXT: and $2, $4, $2 ++; MIPSR6-NEXT: andi $3, $4, 3 ++; MIPSR6-NEXT: xori $3, $3, 2 ++; MIPSR6-NEXT: sll $3, $3, 3 ++; MIPSR6-NEXT: ori $4, $zero, 65535 ++; MIPSR6-NEXT: sllv $4, $4, $3 ++; MIPSR6-NEXT: nor $6, $zero, $4 ++; MIPSR6-NEXT: sllv $5, $5, $3 ++; MIPSR6-NEXT: $BB5_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $8, 0($2) ++; MIPSR6-NEXT: slt $11, $8, $5 ++; MIPSR6-NEXT: selnez $9, $8, $11 ++; MIPSR6-NEXT: seleqz $11, $5, $11 ++; MIPSR6-NEXT: or $9, $9, $11 ++; MIPSR6-NEXT: and $9, $9, $4 ++; MIPSR6-NEXT: and $10, $8, $6 ++; MIPSR6-NEXT: or $10, $10, $9 ++; MIPSR6-NEXT: sc $10, 0($2) ++; MIPSR6-NEXT: beqzc $10, $BB5_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: and $7, $8, $4 ++; MIPSR6-NEXT: srlv $7, $7, $3 ++; MIPSR6-NEXT: seh $7, $7 ++; MIPSR6-NEXT: # %bb.3: # %entry ++; MIPSR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSR6-NEXT: # %bb.4: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSR6-NEXT: addiu $sp, $sp, 8 ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_min_16: ++; MM: # %bb.0: # %entry ++; MM-NEXT: addiu $sp, $sp, -8 ++; MM-NEXT: .cfi_def_cfa_offset 8 ++; MM-NEXT: move $1, $5 ++; MM-NEXT: sync ++; MM-NEXT: addiu $2, $zero, -4 ++; MM-NEXT: and $2, $4, $2 ++; MM-NEXT: andi $3, $4, 3 ++; MM-NEXT: xori $3, $3, 2 ++; MM-NEXT: sll $3, $3, 3 ++; MM-NEXT: ori $4, $zero, 65535 ++; MM-NEXT: sllv $4, $4, $3 ++; MM-NEXT: nor $6, $zero, $4 ++; MM-NEXT: sllv $5, $5, $3 ++; MM-NEXT: $BB5_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $8, 0($2) ++; MM-NEXT: slt $11, $8, $5 ++; MM-NEXT: or $9, $8, $zero ++; MM-NEXT: movz $9, $5, $11 ++; MM-NEXT: and $9, $9, $4 ++; MM-NEXT: and $10, $8, $6 ++; MM-NEXT: or $10, $10, $9 ++; MM-NEXT: sc $10, 0($2) ++; MM-NEXT: beqzc $10, $BB5_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: and $7, $8, $4 ++; MM-NEXT: srlv $7, $7, $3 ++; MM-NEXT: seh $7, $7 ++; MM-NEXT: # %bb.3: # %entry ++; MM-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MM-NEXT: # %bb.4: # %entry ++; MM-NEXT: sync ++; MM-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MM-NEXT: addiusp 8 ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_min_16: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: addiu $sp, $sp, -8 ++; MMR6-NEXT: .cfi_def_cfa_offset 8 ++; MMR6-NEXT: move $1, $5 ++; MMR6-NEXT: sync ++; MMR6-NEXT: addiu $2, $zero, -4 ++; MMR6-NEXT: and $2, $4, $2 ++; MMR6-NEXT: andi $3, $4, 3 ++; MMR6-NEXT: xori $3, $3, 2 ++; MMR6-NEXT: sll $3, $3, 3 ++; MMR6-NEXT: ori $4, $zero, 65535 ++; MMR6-NEXT: sllv $4, $4, $3 ++; MMR6-NEXT: nor $6, $zero, $4 ++; MMR6-NEXT: sllv $5, $5, $3 ++; MMR6-NEXT: $BB5_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $8, 0($2) ++; MMR6-NEXT: slt $11, $8, $5 ++; MMR6-NEXT: selnez $9, $8, $11 ++; MMR6-NEXT: seleqz $11, $5, $11 ++; MMR6-NEXT: or $9, $9, $11 ++; MMR6-NEXT: and $9, $9, $4 ++; MMR6-NEXT: and $10, $8, $6 ++; MMR6-NEXT: or $10, $10, $9 ++; MMR6-NEXT: sc $10, 0($2) ++; MMR6-NEXT: beqc $10, $zero, $BB5_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: and $7, $8, $4 ++; MMR6-NEXT: srlv $7, $7, $3 ++; MMR6-NEXT: seh $7, $7 ++; MMR6-NEXT: # %bb.3: # %entry ++; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMR6-NEXT: # %bb.4: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMR6-NEXT: addiu $sp, $sp, 8 ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_min_16: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: addiu $sp, $sp, -8 ++; MIPSEL-NEXT: .cfi_def_cfa_offset 8 ++; MIPSEL-NEXT: move $1, $5 ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: addiu $2, $zero, -4 ++; MIPSEL-NEXT: and $2, $4, $2 ++; MIPSEL-NEXT: andi $3, $4, 3 ++; MIPSEL-NEXT: sll $3, $3, 3 ++; MIPSEL-NEXT: ori $4, $zero, 65535 ++; MIPSEL-NEXT: sllv $4, $4, $3 ++; MIPSEL-NEXT: nor $6, $zero, $4 ++; MIPSEL-NEXT: sllv $5, $5, $3 ++; MIPSEL-NEXT: $BB5_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $8, 0($2) ++; MIPSEL-NEXT: and $8, $8, $4 ++; MIPSEL-NEXT: and $5, $5, $4 ++; MIPSEL-NEXT: slt $11, $8, $5 ++; MIPSEL-NEXT: move $9, $8 ++; MIPSEL-NEXT: movz $9, $5, $11 ++; MIPSEL-NEXT: and $9, $9, $4 ++; MIPSEL-NEXT: and $10, $8, $6 ++; MIPSEL-NEXT: or $10, $10, $9 ++; MIPSEL-NEXT: sc $10, 0($2) ++; MIPSEL-NEXT: beqz $10, $BB5_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: and $7, $8, $4 ++; MIPSEL-NEXT: srlv $7, $7, $3 ++; MIPSEL-NEXT: seh $7, $7 ++; MIPSEL-NEXT: # %bb.3: # %entry ++; MIPSEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSEL-NEXT: # %bb.4: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSEL-NEXT: addiu $sp, $sp, 8 ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_min_16: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: addiu $sp, $sp, -8 ++; MIPSELR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSELR6-NEXT: move $1, $5 ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: addiu $2, $zero, -4 ++; MIPSELR6-NEXT: and $2, $4, $2 ++; MIPSELR6-NEXT: andi $3, $4, 3 ++; MIPSELR6-NEXT: sll $3, $3, 3 ++; MIPSELR6-NEXT: ori $4, $zero, 65535 ++; MIPSELR6-NEXT: sllv $4, $4, $3 ++; MIPSELR6-NEXT: nor $6, $zero, $4 ++; MIPSELR6-NEXT: sllv $5, $5, $3 ++; MIPSELR6-NEXT: $BB5_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $8, 0($2) ++; MIPSELR6-NEXT: and $8, $8, $4 ++; MIPSELR6-NEXT: and $5, $5, $4 ++; MIPSELR6-NEXT: slt $11, $8, $5 ++; MIPSELR6-NEXT: selnez $9, $8, $11 ++; MIPSELR6-NEXT: seleqz $11, $5, $11 ++; MIPSELR6-NEXT: or $9, $9, $11 ++; MIPSELR6-NEXT: and $9, $9, $4 ++; MIPSELR6-NEXT: and $10, $8, $6 ++; MIPSELR6-NEXT: or $10, $10, $9 ++; MIPSELR6-NEXT: sc $10, 0($2) ++; MIPSELR6-NEXT: beqzc $10, $BB5_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: and $7, $8, $4 ++; MIPSELR6-NEXT: srlv $7, $7, $3 ++; MIPSELR6-NEXT: seh $7, $7 ++; MIPSELR6-NEXT: # %bb.3: # %entry ++; MIPSELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSELR6-NEXT: # %bb.4: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSELR6-NEXT: addiu $sp, $sp, 8 ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_min_16: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: addiu $sp, $sp, -8 ++; MMEL-NEXT: .cfi_def_cfa_offset 8 ++; MMEL-NEXT: move $1, $5 ++; MMEL-NEXT: sync ++; MMEL-NEXT: addiu $2, $zero, -4 ++; MMEL-NEXT: and $2, $4, $2 ++; MMEL-NEXT: andi $3, $4, 3 ++; MMEL-NEXT: sll $3, $3, 3 ++; MMEL-NEXT: ori $4, $zero, 65535 ++; MMEL-NEXT: sllv $4, $4, $3 ++; MMEL-NEXT: nor $6, $zero, $4 ++; MMEL-NEXT: sllv $5, $5, $3 ++; MMEL-NEXT: $BB5_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $8, 0($2) ++; MMEL-NEXT: and $8, $8, $4 ++; MMEL-NEXT: and $5, $5, $4 ++; MMEL-NEXT: slt $11, $8, $5 ++; MMEL-NEXT: or $9, $8, $zero ++; MMEL-NEXT: movz $9, $5, $11 ++; MMEL-NEXT: and $9, $9, $4 ++; MMEL-NEXT: and $10, $8, $6 ++; MMEL-NEXT: or $10, $10, $9 ++; MMEL-NEXT: sc $10, 0($2) ++; MMEL-NEXT: beqzc $10, $BB5_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: and $7, $8, $4 ++; MMEL-NEXT: srlv $7, $7, $3 ++; MMEL-NEXT: seh $7, $7 ++; MMEL-NEXT: # %bb.3: # %entry ++; MMEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMEL-NEXT: # %bb.4: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMEL-NEXT: addiusp 8 ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_min_16: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: addiu $sp, $sp, -8 ++; MMELR6-NEXT: .cfi_def_cfa_offset 8 ++; MMELR6-NEXT: move $1, $5 ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: addiu $2, $zero, -4 ++; MMELR6-NEXT: and $2, $4, $2 ++; MMELR6-NEXT: andi $3, $4, 3 ++; MMELR6-NEXT: sll $3, $3, 3 ++; MMELR6-NEXT: ori $4, $zero, 65535 ++; MMELR6-NEXT: sllv $4, $4, $3 ++; MMELR6-NEXT: nor $6, $zero, $4 ++; MMELR6-NEXT: sllv $5, $5, $3 ++; MMELR6-NEXT: $BB5_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $8, 0($2) ++; MMELR6-NEXT: and $8, $8, $4 ++; MMELR6-NEXT: and $5, $5, $4 ++; MMELR6-NEXT: slt $11, $8, $5 ++; MMELR6-NEXT: selnez $9, $8, $11 ++; MMELR6-NEXT: seleqz $11, $5, $11 ++; MMELR6-NEXT: or $9, $9, $11 ++; MMELR6-NEXT: and $9, $9, $4 ++; MMELR6-NEXT: and $10, $8, $6 ++; MMELR6-NEXT: or $10, $10, $9 ++; MMELR6-NEXT: sc $10, 0($2) ++; MMELR6-NEXT: beqc $10, $zero, $BB5_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: and $7, $8, $4 ++; MMELR6-NEXT: srlv $7, $7, $3 ++; MMELR6-NEXT: seh $7, $7 ++; MMELR6-NEXT: # %bb.3: # %entry ++; MMELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMELR6-NEXT: # %bb.4: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMELR6-NEXT: addiu $sp, $sp, 8 ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_min_16: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: daddiu $sp, $sp, -16 ++; MIPS64-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: daddiu $1, $zero, -4 ++; MIPS64-NEXT: and $1, $4, $1 ++; MIPS64-NEXT: andi $2, $4, 3 ++; MIPS64-NEXT: xori $2, $2, 2 ++; MIPS64-NEXT: sll $2, $2, 3 ++; MIPS64-NEXT: ori $3, $zero, 65535 ++; MIPS64-NEXT: sllv $3, $3, $2 ++; MIPS64-NEXT: nor $6, $zero, $3 ++; MIPS64-NEXT: sllv $5, $5, $2 ++; MIPS64-NEXT: .LBB5_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $8, 0($1) ++; MIPS64-NEXT: slt $11, $8, $5 ++; MIPS64-NEXT: move $9, $8 ++; MIPS64-NEXT: movz $9, $5, $11 ++; MIPS64-NEXT: and $9, $9, $3 ++; MIPS64-NEXT: and $10, $8, $6 ++; MIPS64-NEXT: or $10, $10, $9 ++; MIPS64-NEXT: sc $10, 0($1) ++; MIPS64-NEXT: beqz $10, .LBB5_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: and $7, $8, $3 ++; MIPS64-NEXT: srlv $7, $7, $2 ++; MIPS64-NEXT: seh $7, $7 ++; MIPS64-NEXT: # %bb.3: # %entry ++; MIPS64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64-NEXT: # %bb.4: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64-NEXT: daddiu $sp, $sp, 16 ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_min_16: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64R6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: daddiu $1, $zero, -4 ++; MIPS64R6-NEXT: and $1, $4, $1 ++; MIPS64R6-NEXT: andi $2, $4, 3 ++; MIPS64R6-NEXT: xori $2, $2, 2 ++; MIPS64R6-NEXT: sll $2, $2, 3 ++; MIPS64R6-NEXT: ori $3, $zero, 65535 ++; MIPS64R6-NEXT: sllv $3, $3, $2 ++; MIPS64R6-NEXT: nor $6, $zero, $3 ++; MIPS64R6-NEXT: sllv $5, $5, $2 ++; MIPS64R6-NEXT: .LBB5_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $8, 0($1) ++; MIPS64R6-NEXT: slt $11, $8, $5 ++; MIPS64R6-NEXT: selnez $9, $8, $11 ++; MIPS64R6-NEXT: seleqz $11, $5, $11 ++; MIPS64R6-NEXT: or $9, $9, $11 ++; MIPS64R6-NEXT: and $9, $9, $3 ++; MIPS64R6-NEXT: and $10, $8, $6 ++; MIPS64R6-NEXT: or $10, $10, $9 ++; MIPS64R6-NEXT: sc $10, 0($1) ++; MIPS64R6-NEXT: beqzc $10, .LBB5_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: and $7, $8, $3 ++; MIPS64R6-NEXT: srlv $7, $7, $2 ++; MIPS64R6-NEXT: seh $7, $7 ++; MIPS64R6-NEXT: # %bb.3: # %entry ++; MIPS64R6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64R6-NEXT: # %bb.4: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64R6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_min_16: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: daddiu $sp, $sp, -16 ++; MIPS64EL-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: daddiu $1, $zero, -4 ++; MIPS64EL-NEXT: and $1, $4, $1 ++; MIPS64EL-NEXT: andi $2, $4, 3 ++; MIPS64EL-NEXT: sll $2, $2, 3 ++; MIPS64EL-NEXT: ori $3, $zero, 65535 ++; MIPS64EL-NEXT: sllv $3, $3, $2 ++; MIPS64EL-NEXT: nor $6, $zero, $3 ++; MIPS64EL-NEXT: sllv $5, $5, $2 ++; MIPS64EL-NEXT: .LBB5_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $8, 0($1) ++; MIPS64EL-NEXT: and $8, $8, $3 ++; MIPS64EL-NEXT: and $5, $5, $3 ++; MIPS64EL-NEXT: slt $11, $8, $5 ++; MIPS64EL-NEXT: move $9, $8 ++; MIPS64EL-NEXT: movz $9, $5, $11 ++; MIPS64EL-NEXT: and $9, $9, $3 ++; MIPS64EL-NEXT: and $10, $8, $6 ++; MIPS64EL-NEXT: or $10, $10, $9 ++; MIPS64EL-NEXT: sc $10, 0($1) ++; MIPS64EL-NEXT: beqz $10, .LBB5_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: and $7, $8, $3 ++; MIPS64EL-NEXT: srlv $7, $7, $2 ++; MIPS64EL-NEXT: seh $7, $7 ++; MIPS64EL-NEXT: # %bb.3: # %entry ++; MIPS64EL-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64EL-NEXT: # %bb.4: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64EL-NEXT: daddiu $sp, $sp, 16 ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_min_16: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64ELR6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: daddiu $1, $zero, -4 ++; MIPS64ELR6-NEXT: and $1, $4, $1 ++; MIPS64ELR6-NEXT: andi $2, $4, 3 ++; MIPS64ELR6-NEXT: sll $2, $2, 3 ++; MIPS64ELR6-NEXT: ori $3, $zero, 65535 ++; MIPS64ELR6-NEXT: sllv $3, $3, $2 ++; MIPS64ELR6-NEXT: nor $6, $zero, $3 ++; MIPS64ELR6-NEXT: sllv $5, $5, $2 ++; MIPS64ELR6-NEXT: .LBB5_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $8, 0($1) ++; MIPS64ELR6-NEXT: and $8, $8, $3 ++; MIPS64ELR6-NEXT: and $5, $5, $3 ++; MIPS64ELR6-NEXT: slt $11, $8, $5 ++; MIPS64ELR6-NEXT: selnez $9, $8, $11 ++; MIPS64ELR6-NEXT: seleqz $11, $5, $11 ++; MIPS64ELR6-NEXT: or $9, $9, $11 ++; MIPS64ELR6-NEXT: and $9, $9, $3 ++; MIPS64ELR6-NEXT: and $10, $8, $6 ++; MIPS64ELR6-NEXT: or $10, $10, $9 ++; MIPS64ELR6-NEXT: sc $10, 0($1) ++; MIPS64ELR6-NEXT: beqzc $10, .LBB5_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: and $7, $8, $3 ++; MIPS64ELR6-NEXT: srlv $7, $7, $2 ++; MIPS64ELR6-NEXT: seh $7, $7 ++; MIPS64ELR6-NEXT: # %bb.3: # %entry ++; MIPS64ELR6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64ELR6-NEXT: # %bb.4: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw min i16* %ptr, i16 %val seq_cst ++ ret i16 %0 ++} ++ ++define i16 @test_umax_16(i16* nocapture %ptr, i16 signext %val) { ++; MIPS-LABEL: test_umax_16: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: addiu $sp, $sp, -8 ++; MIPS-NEXT: .cfi_def_cfa_offset 8 ++; MIPS-NEXT: move $1, $5 ++; MIPS-NEXT: sync ++; MIPS-NEXT: addiu $2, $zero, -4 ++; MIPS-NEXT: and $2, $4, $2 ++; MIPS-NEXT: andi $3, $4, 3 ++; MIPS-NEXT: xori $3, $3, 2 ++; MIPS-NEXT: sll $3, $3, 3 ++; MIPS-NEXT: ori $4, $zero, 65535 ++; MIPS-NEXT: sllv $4, $4, $3 ++; MIPS-NEXT: nor $6, $zero, $4 ++; MIPS-NEXT: sllv $5, $5, $3 ++; MIPS-NEXT: $BB6_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $8, 0($2) ++; MIPS-NEXT: sltu $11, $8, $5 ++; MIPS-NEXT: move $9, $8 ++; MIPS-NEXT: movn $9, $5, $11 ++; MIPS-NEXT: and $9, $9, $4 ++; MIPS-NEXT: and $10, $8, $6 ++; MIPS-NEXT: or $10, $10, $9 ++; MIPS-NEXT: sc $10, 0($2) ++; MIPS-NEXT: beqz $10, $BB6_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: and $7, $8, $4 ++; MIPS-NEXT: srlv $7, $7, $3 ++; MIPS-NEXT: seh $7, $7 ++; MIPS-NEXT: # %bb.3: # %entry ++; MIPS-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPS-NEXT: # %bb.4: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPS-NEXT: addiu $sp, $sp, 8 ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_umax_16: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: addiu $sp, $sp, -8 ++; MIPSR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSR6-NEXT: move $1, $5 ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: addiu $2, $zero, -4 ++; MIPSR6-NEXT: and $2, $4, $2 ++; MIPSR6-NEXT: andi $3, $4, 3 ++; MIPSR6-NEXT: xori $3, $3, 2 ++; MIPSR6-NEXT: sll $3, $3, 3 ++; MIPSR6-NEXT: ori $4, $zero, 65535 ++; MIPSR6-NEXT: sllv $4, $4, $3 ++; MIPSR6-NEXT: nor $6, $zero, $4 ++; MIPSR6-NEXT: sllv $5, $5, $3 ++; MIPSR6-NEXT: $BB6_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $8, 0($2) ++; MIPSR6-NEXT: sltu $11, $8, $5 ++; MIPSR6-NEXT: seleqz $9, $8, $11 ++; MIPSR6-NEXT: selnez $11, $5, $11 ++; MIPSR6-NEXT: or $9, $9, $11 ++; MIPSR6-NEXT: and $9, $9, $4 ++; MIPSR6-NEXT: and $10, $8, $6 ++; MIPSR6-NEXT: or $10, $10, $9 ++; MIPSR6-NEXT: sc $10, 0($2) ++; MIPSR6-NEXT: beqzc $10, $BB6_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: and $7, $8, $4 ++; MIPSR6-NEXT: srlv $7, $7, $3 ++; MIPSR6-NEXT: seh $7, $7 ++; MIPSR6-NEXT: # %bb.3: # %entry ++; MIPSR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSR6-NEXT: # %bb.4: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSR6-NEXT: addiu $sp, $sp, 8 ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_umax_16: ++; MM: # %bb.0: # %entry ++; MM-NEXT: addiu $sp, $sp, -8 ++; MM-NEXT: .cfi_def_cfa_offset 8 ++; MM-NEXT: move $1, $5 ++; MM-NEXT: sync ++; MM-NEXT: addiu $2, $zero, -4 ++; MM-NEXT: and $2, $4, $2 ++; MM-NEXT: andi $3, $4, 3 ++; MM-NEXT: xori $3, $3, 2 ++; MM-NEXT: sll $3, $3, 3 ++; MM-NEXT: ori $4, $zero, 65535 ++; MM-NEXT: sllv $4, $4, $3 ++; MM-NEXT: nor $6, $zero, $4 ++; MM-NEXT: sllv $5, $5, $3 ++; MM-NEXT: $BB6_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $8, 0($2) ++; MM-NEXT: sltu $11, $8, $5 ++; MM-NEXT: or $9, $8, $zero ++; MM-NEXT: movn $9, $5, $11 ++; MM-NEXT: and $9, $9, $4 ++; MM-NEXT: and $10, $8, $6 ++; MM-NEXT: or $10, $10, $9 ++; MM-NEXT: sc $10, 0($2) ++; MM-NEXT: beqzc $10, $BB6_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: and $7, $8, $4 ++; MM-NEXT: srlv $7, $7, $3 ++; MM-NEXT: seh $7, $7 ++; MM-NEXT: # %bb.3: # %entry ++; MM-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MM-NEXT: # %bb.4: # %entry ++; MM-NEXT: sync ++; MM-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MM-NEXT: addiusp 8 ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_umax_16: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: addiu $sp, $sp, -8 ++; MMR6-NEXT: .cfi_def_cfa_offset 8 ++; MMR6-NEXT: move $1, $5 ++; MMR6-NEXT: sync ++; MMR6-NEXT: addiu $2, $zero, -4 ++; MMR6-NEXT: and $2, $4, $2 ++; MMR6-NEXT: andi $3, $4, 3 ++; MMR6-NEXT: xori $3, $3, 2 ++; MMR6-NEXT: sll $3, $3, 3 ++; MMR6-NEXT: ori $4, $zero, 65535 ++; MMR6-NEXT: sllv $4, $4, $3 ++; MMR6-NEXT: nor $6, $zero, $4 ++; MMR6-NEXT: sllv $5, $5, $3 ++; MMR6-NEXT: $BB6_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $8, 0($2) ++; MMR6-NEXT: sltu $11, $8, $5 ++; MMR6-NEXT: seleqz $9, $8, $11 ++; MMR6-NEXT: selnez $11, $5, $11 ++; MMR6-NEXT: or $9, $9, $11 ++; MMR6-NEXT: and $9, $9, $4 ++; MMR6-NEXT: and $10, $8, $6 ++; MMR6-NEXT: or $10, $10, $9 ++; MMR6-NEXT: sc $10, 0($2) ++; MMR6-NEXT: beqc $10, $zero, $BB6_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: and $7, $8, $4 ++; MMR6-NEXT: srlv $7, $7, $3 ++; MMR6-NEXT: seh $7, $7 ++; MMR6-NEXT: # %bb.3: # %entry ++; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMR6-NEXT: # %bb.4: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMR6-NEXT: addiu $sp, $sp, 8 ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_umax_16: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: addiu $sp, $sp, -8 ++; MIPSEL-NEXT: .cfi_def_cfa_offset 8 ++; MIPSEL-NEXT: move $1, $5 ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: addiu $2, $zero, -4 ++; MIPSEL-NEXT: and $2, $4, $2 ++; MIPSEL-NEXT: andi $3, $4, 3 ++; MIPSEL-NEXT: sll $3, $3, 3 ++; MIPSEL-NEXT: ori $4, $zero, 65535 ++; MIPSEL-NEXT: sllv $4, $4, $3 ++; MIPSEL-NEXT: nor $6, $zero, $4 ++; MIPSEL-NEXT: sllv $5, $5, $3 ++; MIPSEL-NEXT: $BB6_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $8, 0($2) ++; MIPSEL-NEXT: and $8, $8, $4 ++; MIPSEL-NEXT: and $5, $5, $4 ++; MIPSEL-NEXT: sltu $11, $8, $5 ++; MIPSEL-NEXT: move $9, $8 ++; MIPSEL-NEXT: movn $9, $5, $11 ++; MIPSEL-NEXT: and $9, $9, $4 ++; MIPSEL-NEXT: and $10, $8, $6 ++; MIPSEL-NEXT: or $10, $10, $9 ++; MIPSEL-NEXT: sc $10, 0($2) ++; MIPSEL-NEXT: beqz $10, $BB6_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: and $7, $8, $4 ++; MIPSEL-NEXT: srlv $7, $7, $3 ++; MIPSEL-NEXT: seh $7, $7 ++; MIPSEL-NEXT: # %bb.3: # %entry ++; MIPSEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSEL-NEXT: # %bb.4: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSEL-NEXT: addiu $sp, $sp, 8 ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_umax_16: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: addiu $sp, $sp, -8 ++; MIPSELR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSELR6-NEXT: move $1, $5 ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: addiu $2, $zero, -4 ++; MIPSELR6-NEXT: and $2, $4, $2 ++; MIPSELR6-NEXT: andi $3, $4, 3 ++; MIPSELR6-NEXT: sll $3, $3, 3 ++; MIPSELR6-NEXT: ori $4, $zero, 65535 ++; MIPSELR6-NEXT: sllv $4, $4, $3 ++; MIPSELR6-NEXT: nor $6, $zero, $4 ++; MIPSELR6-NEXT: sllv $5, $5, $3 ++; MIPSELR6-NEXT: $BB6_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $8, 0($2) ++; MIPSELR6-NEXT: and $8, $8, $4 ++; MIPSELR6-NEXT: and $5, $5, $4 ++; MIPSELR6-NEXT: sltu $11, $8, $5 ++; MIPSELR6-NEXT: seleqz $9, $8, $11 ++; MIPSELR6-NEXT: selnez $11, $5, $11 ++; MIPSELR6-NEXT: or $9, $9, $11 ++; MIPSELR6-NEXT: and $9, $9, $4 ++; MIPSELR6-NEXT: and $10, $8, $6 ++; MIPSELR6-NEXT: or $10, $10, $9 ++; MIPSELR6-NEXT: sc $10, 0($2) ++; MIPSELR6-NEXT: beqzc $10, $BB6_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: and $7, $8, $4 ++; MIPSELR6-NEXT: srlv $7, $7, $3 ++; MIPSELR6-NEXT: seh $7, $7 ++; MIPSELR6-NEXT: # %bb.3: # %entry ++; MIPSELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSELR6-NEXT: # %bb.4: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSELR6-NEXT: addiu $sp, $sp, 8 ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_umax_16: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: addiu $sp, $sp, -8 ++; MMEL-NEXT: .cfi_def_cfa_offset 8 ++; MMEL-NEXT: move $1, $5 ++; MMEL-NEXT: sync ++; MMEL-NEXT: addiu $2, $zero, -4 ++; MMEL-NEXT: and $2, $4, $2 ++; MMEL-NEXT: andi $3, $4, 3 ++; MMEL-NEXT: sll $3, $3, 3 ++; MMEL-NEXT: ori $4, $zero, 65535 ++; MMEL-NEXT: sllv $4, $4, $3 ++; MMEL-NEXT: nor $6, $zero, $4 ++; MMEL-NEXT: sllv $5, $5, $3 ++; MMEL-NEXT: $BB6_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $8, 0($2) ++; MMEL-NEXT: and $8, $8, $4 ++; MMEL-NEXT: and $5, $5, $4 ++; MMEL-NEXT: sltu $11, $8, $5 ++; MMEL-NEXT: or $9, $8, $zero ++; MMEL-NEXT: movn $9, $5, $11 ++; MMEL-NEXT: and $9, $9, $4 ++; MMEL-NEXT: and $10, $8, $6 ++; MMEL-NEXT: or $10, $10, $9 ++; MMEL-NEXT: sc $10, 0($2) ++; MMEL-NEXT: beqzc $10, $BB6_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: and $7, $8, $4 ++; MMEL-NEXT: srlv $7, $7, $3 ++; MMEL-NEXT: seh $7, $7 ++; MMEL-NEXT: # %bb.3: # %entry ++; MMEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMEL-NEXT: # %bb.4: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMEL-NEXT: addiusp 8 ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_umax_16: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: addiu $sp, $sp, -8 ++; MMELR6-NEXT: .cfi_def_cfa_offset 8 ++; MMELR6-NEXT: move $1, $5 ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: addiu $2, $zero, -4 ++; MMELR6-NEXT: and $2, $4, $2 ++; MMELR6-NEXT: andi $3, $4, 3 ++; MMELR6-NEXT: sll $3, $3, 3 ++; MMELR6-NEXT: ori $4, $zero, 65535 ++; MMELR6-NEXT: sllv $4, $4, $3 ++; MMELR6-NEXT: nor $6, $zero, $4 ++; MMELR6-NEXT: sllv $5, $5, $3 ++; MMELR6-NEXT: $BB6_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $8, 0($2) ++; MMELR6-NEXT: and $8, $8, $4 ++; MMELR6-NEXT: and $5, $5, $4 ++; MMELR6-NEXT: sltu $11, $8, $5 ++; MMELR6-NEXT: seleqz $9, $8, $11 ++; MMELR6-NEXT: selnez $11, $5, $11 ++; MMELR6-NEXT: or $9, $9, $11 ++; MMELR6-NEXT: and $9, $9, $4 ++; MMELR6-NEXT: and $10, $8, $6 ++; MMELR6-NEXT: or $10, $10, $9 ++; MMELR6-NEXT: sc $10, 0($2) ++; MMELR6-NEXT: beqc $10, $zero, $BB6_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: and $7, $8, $4 ++; MMELR6-NEXT: srlv $7, $7, $3 ++; MMELR6-NEXT: seh $7, $7 ++; MMELR6-NEXT: # %bb.3: # %entry ++; MMELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMELR6-NEXT: # %bb.4: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMELR6-NEXT: addiu $sp, $sp, 8 ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_umax_16: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: daddiu $sp, $sp, -16 ++; MIPS64-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: daddiu $1, $zero, -4 ++; MIPS64-NEXT: and $1, $4, $1 ++; MIPS64-NEXT: andi $2, $4, 3 ++; MIPS64-NEXT: xori $2, $2, 2 ++; MIPS64-NEXT: sll $2, $2, 3 ++; MIPS64-NEXT: ori $3, $zero, 65535 ++; MIPS64-NEXT: sllv $3, $3, $2 ++; MIPS64-NEXT: nor $6, $zero, $3 ++; MIPS64-NEXT: sllv $5, $5, $2 ++; MIPS64-NEXT: .LBB6_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $8, 0($1) ++; MIPS64-NEXT: sltu $11, $8, $5 ++; MIPS64-NEXT: move $9, $8 ++; MIPS64-NEXT: movn $9, $5, $11 ++; MIPS64-NEXT: and $9, $9, $3 ++; MIPS64-NEXT: and $10, $8, $6 ++; MIPS64-NEXT: or $10, $10, $9 ++; MIPS64-NEXT: sc $10, 0($1) ++; MIPS64-NEXT: beqz $10, .LBB6_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: and $7, $8, $3 ++; MIPS64-NEXT: srlv $7, $7, $2 ++; MIPS64-NEXT: seh $7, $7 ++; MIPS64-NEXT: # %bb.3: # %entry ++; MIPS64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64-NEXT: # %bb.4: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64-NEXT: daddiu $sp, $sp, 16 ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_umax_16: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64R6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: daddiu $1, $zero, -4 ++; MIPS64R6-NEXT: and $1, $4, $1 ++; MIPS64R6-NEXT: andi $2, $4, 3 ++; MIPS64R6-NEXT: xori $2, $2, 2 ++; MIPS64R6-NEXT: sll $2, $2, 3 ++; MIPS64R6-NEXT: ori $3, $zero, 65535 ++; MIPS64R6-NEXT: sllv $3, $3, $2 ++; MIPS64R6-NEXT: nor $6, $zero, $3 ++; MIPS64R6-NEXT: sllv $5, $5, $2 ++; MIPS64R6-NEXT: .LBB6_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $8, 0($1) ++; MIPS64R6-NEXT: sltu $11, $8, $5 ++; MIPS64R6-NEXT: seleqz $9, $8, $11 ++; MIPS64R6-NEXT: selnez $11, $5, $11 ++; MIPS64R6-NEXT: or $9, $9, $11 ++; MIPS64R6-NEXT: and $9, $9, $3 ++; MIPS64R6-NEXT: and $10, $8, $6 ++; MIPS64R6-NEXT: or $10, $10, $9 ++; MIPS64R6-NEXT: sc $10, 0($1) ++; MIPS64R6-NEXT: beqzc $10, .LBB6_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: and $7, $8, $3 ++; MIPS64R6-NEXT: srlv $7, $7, $2 ++; MIPS64R6-NEXT: seh $7, $7 ++; MIPS64R6-NEXT: # %bb.3: # %entry ++; MIPS64R6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64R6-NEXT: # %bb.4: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64R6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_umax_16: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: daddiu $sp, $sp, -16 ++; MIPS64EL-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: daddiu $1, $zero, -4 ++; MIPS64EL-NEXT: and $1, $4, $1 ++; MIPS64EL-NEXT: andi $2, $4, 3 ++; MIPS64EL-NEXT: sll $2, $2, 3 ++; MIPS64EL-NEXT: ori $3, $zero, 65535 ++; MIPS64EL-NEXT: sllv $3, $3, $2 ++; MIPS64EL-NEXT: nor $6, $zero, $3 ++; MIPS64EL-NEXT: sllv $5, $5, $2 ++; MIPS64EL-NEXT: .LBB6_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $8, 0($1) ++; MIPS64EL-NEXT: and $8, $8, $3 ++; MIPS64EL-NEXT: and $5, $5, $3 ++; MIPS64EL-NEXT: sltu $11, $8, $5 ++; MIPS64EL-NEXT: move $9, $8 ++; MIPS64EL-NEXT: movn $9, $5, $11 ++; MIPS64EL-NEXT: and $9, $9, $3 ++; MIPS64EL-NEXT: and $10, $8, $6 ++; MIPS64EL-NEXT: or $10, $10, $9 ++; MIPS64EL-NEXT: sc $10, 0($1) ++; MIPS64EL-NEXT: beqz $10, .LBB6_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: and $7, $8, $3 ++; MIPS64EL-NEXT: srlv $7, $7, $2 ++; MIPS64EL-NEXT: seh $7, $7 ++; MIPS64EL-NEXT: # %bb.3: # %entry ++; MIPS64EL-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64EL-NEXT: # %bb.4: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64EL-NEXT: daddiu $sp, $sp, 16 ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_umax_16: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64ELR6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: daddiu $1, $zero, -4 ++; MIPS64ELR6-NEXT: and $1, $4, $1 ++; MIPS64ELR6-NEXT: andi $2, $4, 3 ++; MIPS64ELR6-NEXT: sll $2, $2, 3 ++; MIPS64ELR6-NEXT: ori $3, $zero, 65535 ++; MIPS64ELR6-NEXT: sllv $3, $3, $2 ++; MIPS64ELR6-NEXT: nor $6, $zero, $3 ++; MIPS64ELR6-NEXT: sllv $5, $5, $2 ++; MIPS64ELR6-NEXT: .LBB6_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $8, 0($1) ++; MIPS64ELR6-NEXT: and $8, $8, $3 ++; MIPS64ELR6-NEXT: and $5, $5, $3 ++; MIPS64ELR6-NEXT: sltu $11, $8, $5 ++; MIPS64ELR6-NEXT: seleqz $9, $8, $11 ++; MIPS64ELR6-NEXT: selnez $11, $5, $11 ++; MIPS64ELR6-NEXT: or $9, $9, $11 ++; MIPS64ELR6-NEXT: and $9, $9, $3 ++; MIPS64ELR6-NEXT: and $10, $8, $6 ++; MIPS64ELR6-NEXT: or $10, $10, $9 ++; MIPS64ELR6-NEXT: sc $10, 0($1) ++; MIPS64ELR6-NEXT: beqzc $10, .LBB6_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: and $7, $8, $3 ++; MIPS64ELR6-NEXT: srlv $7, $7, $2 ++; MIPS64ELR6-NEXT: seh $7, $7 ++; MIPS64ELR6-NEXT: # %bb.3: # %entry ++; MIPS64ELR6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64ELR6-NEXT: # %bb.4: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw umax i16* %ptr, i16 %val seq_cst ++ ret i16 %0 ++} ++ ++define i16 @test_umin_16(i16* nocapture %ptr, i16 signext %val) { ++; MIPS-LABEL: test_umin_16: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: addiu $sp, $sp, -8 ++; MIPS-NEXT: .cfi_def_cfa_offset 8 ++; MIPS-NEXT: move $1, $5 ++; MIPS-NEXT: sync ++; MIPS-NEXT: addiu $2, $zero, -4 ++; MIPS-NEXT: and $2, $4, $2 ++; MIPS-NEXT: andi $3, $4, 3 ++; MIPS-NEXT: xori $3, $3, 2 ++; MIPS-NEXT: sll $3, $3, 3 ++; MIPS-NEXT: ori $4, $zero, 65535 ++; MIPS-NEXT: sllv $4, $4, $3 ++; MIPS-NEXT: nor $6, $zero, $4 ++; MIPS-NEXT: sllv $5, $5, $3 ++; MIPS-NEXT: $BB7_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $8, 0($2) ++; MIPS-NEXT: sltu $11, $8, $5 ++; MIPS-NEXT: move $9, $8 ++; MIPS-NEXT: movz $9, $5, $11 ++; MIPS-NEXT: and $9, $9, $4 ++; MIPS-NEXT: and $10, $8, $6 ++; MIPS-NEXT: or $10, $10, $9 ++; MIPS-NEXT: sc $10, 0($2) ++; MIPS-NEXT: beqz $10, $BB7_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: and $7, $8, $4 ++; MIPS-NEXT: srlv $7, $7, $3 ++; MIPS-NEXT: seh $7, $7 ++; MIPS-NEXT: # %bb.3: # %entry ++; MIPS-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPS-NEXT: # %bb.4: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPS-NEXT: addiu $sp, $sp, 8 ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_umin_16: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: addiu $sp, $sp, -8 ++; MIPSR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSR6-NEXT: move $1, $5 ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: addiu $2, $zero, -4 ++; MIPSR6-NEXT: and $2, $4, $2 ++; MIPSR6-NEXT: andi $3, $4, 3 ++; MIPSR6-NEXT: xori $3, $3, 2 ++; MIPSR6-NEXT: sll $3, $3, 3 ++; MIPSR6-NEXT: ori $4, $zero, 65535 ++; MIPSR6-NEXT: sllv $4, $4, $3 ++; MIPSR6-NEXT: nor $6, $zero, $4 ++; MIPSR6-NEXT: sllv $5, $5, $3 ++; MIPSR6-NEXT: $BB7_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $8, 0($2) ++; MIPSR6-NEXT: sltu $11, $8, $5 ++; MIPSR6-NEXT: selnez $9, $8, $11 ++; MIPSR6-NEXT: seleqz $11, $5, $11 ++; MIPSR6-NEXT: or $9, $9, $11 ++; MIPSR6-NEXT: and $9, $9, $4 ++; MIPSR6-NEXT: and $10, $8, $6 ++; MIPSR6-NEXT: or $10, $10, $9 ++; MIPSR6-NEXT: sc $10, 0($2) ++; MIPSR6-NEXT: beqzc $10, $BB7_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: and $7, $8, $4 ++; MIPSR6-NEXT: srlv $7, $7, $3 ++; MIPSR6-NEXT: seh $7, $7 ++; MIPSR6-NEXT: # %bb.3: # %entry ++; MIPSR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSR6-NEXT: # %bb.4: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSR6-NEXT: addiu $sp, $sp, 8 ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_umin_16: ++; MM: # %bb.0: # %entry ++; MM-NEXT: addiu $sp, $sp, -8 ++; MM-NEXT: .cfi_def_cfa_offset 8 ++; MM-NEXT: move $1, $5 ++; MM-NEXT: sync ++; MM-NEXT: addiu $2, $zero, -4 ++; MM-NEXT: and $2, $4, $2 ++; MM-NEXT: andi $3, $4, 3 ++; MM-NEXT: xori $3, $3, 2 ++; MM-NEXT: sll $3, $3, 3 ++; MM-NEXT: ori $4, $zero, 65535 ++; MM-NEXT: sllv $4, $4, $3 ++; MM-NEXT: nor $6, $zero, $4 ++; MM-NEXT: sllv $5, $5, $3 ++; MM-NEXT: $BB7_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $8, 0($2) ++; MM-NEXT: sltu $11, $8, $5 ++; MM-NEXT: or $9, $8, $zero ++; MM-NEXT: movz $9, $5, $11 ++; MM-NEXT: and $9, $9, $4 ++; MM-NEXT: and $10, $8, $6 ++; MM-NEXT: or $10, $10, $9 ++; MM-NEXT: sc $10, 0($2) ++; MM-NEXT: beqzc $10, $BB7_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: and $7, $8, $4 ++; MM-NEXT: srlv $7, $7, $3 ++; MM-NEXT: seh $7, $7 ++; MM-NEXT: # %bb.3: # %entry ++; MM-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MM-NEXT: # %bb.4: # %entry ++; MM-NEXT: sync ++; MM-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MM-NEXT: addiusp 8 ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_umin_16: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: addiu $sp, $sp, -8 ++; MMR6-NEXT: .cfi_def_cfa_offset 8 ++; MMR6-NEXT: move $1, $5 ++; MMR6-NEXT: sync ++; MMR6-NEXT: addiu $2, $zero, -4 ++; MMR6-NEXT: and $2, $4, $2 ++; MMR6-NEXT: andi $3, $4, 3 ++; MMR6-NEXT: xori $3, $3, 2 ++; MMR6-NEXT: sll $3, $3, 3 ++; MMR6-NEXT: ori $4, $zero, 65535 ++; MMR6-NEXT: sllv $4, $4, $3 ++; MMR6-NEXT: nor $6, $zero, $4 ++; MMR6-NEXT: sllv $5, $5, $3 ++; MMR6-NEXT: $BB7_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $8, 0($2) ++; MMR6-NEXT: sltu $11, $8, $5 ++; MMR6-NEXT: selnez $9, $8, $11 ++; MMR6-NEXT: seleqz $11, $5, $11 ++; MMR6-NEXT: or $9, $9, $11 ++; MMR6-NEXT: and $9, $9, $4 ++; MMR6-NEXT: and $10, $8, $6 ++; MMR6-NEXT: or $10, $10, $9 ++; MMR6-NEXT: sc $10, 0($2) ++; MMR6-NEXT: beqc $10, $zero, $BB7_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: and $7, $8, $4 ++; MMR6-NEXT: srlv $7, $7, $3 ++; MMR6-NEXT: seh $7, $7 ++; MMR6-NEXT: # %bb.3: # %entry ++; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMR6-NEXT: # %bb.4: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMR6-NEXT: addiu $sp, $sp, 8 ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_umin_16: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: addiu $sp, $sp, -8 ++; MIPSEL-NEXT: .cfi_def_cfa_offset 8 ++; MIPSEL-NEXT: move $1, $5 ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: addiu $2, $zero, -4 ++; MIPSEL-NEXT: and $2, $4, $2 ++; MIPSEL-NEXT: andi $3, $4, 3 ++; MIPSEL-NEXT: sll $3, $3, 3 ++; MIPSEL-NEXT: ori $4, $zero, 65535 ++; MIPSEL-NEXT: sllv $4, $4, $3 ++; MIPSEL-NEXT: nor $6, $zero, $4 ++; MIPSEL-NEXT: sllv $5, $5, $3 ++; MIPSEL-NEXT: $BB7_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $8, 0($2) ++; MIPSEL-NEXT: and $8, $8, $4 ++; MIPSEL-NEXT: and $5, $5, $4 ++; MIPSEL-NEXT: sltu $11, $8, $5 ++; MIPSEL-NEXT: move $9, $8 ++; MIPSEL-NEXT: movz $9, $5, $11 ++; MIPSEL-NEXT: and $9, $9, $4 ++; MIPSEL-NEXT: and $10, $8, $6 ++; MIPSEL-NEXT: or $10, $10, $9 ++; MIPSEL-NEXT: sc $10, 0($2) ++; MIPSEL-NEXT: beqz $10, $BB7_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: and $7, $8, $4 ++; MIPSEL-NEXT: srlv $7, $7, $3 ++; MIPSEL-NEXT: seh $7, $7 ++; MIPSEL-NEXT: # %bb.3: # %entry ++; MIPSEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSEL-NEXT: # %bb.4: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSEL-NEXT: addiu $sp, $sp, 8 ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_umin_16: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: addiu $sp, $sp, -8 ++; MIPSELR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSELR6-NEXT: move $1, $5 ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: addiu $2, $zero, -4 ++; MIPSELR6-NEXT: and $2, $4, $2 ++; MIPSELR6-NEXT: andi $3, $4, 3 ++; MIPSELR6-NEXT: sll $3, $3, 3 ++; MIPSELR6-NEXT: ori $4, $zero, 65535 ++; MIPSELR6-NEXT: sllv $4, $4, $3 ++; MIPSELR6-NEXT: nor $6, $zero, $4 ++; MIPSELR6-NEXT: sllv $5, $5, $3 ++; MIPSELR6-NEXT: $BB7_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $8, 0($2) ++; MIPSELR6-NEXT: and $8, $8, $4 ++; MIPSELR6-NEXT: and $5, $5, $4 ++; MIPSELR6-NEXT: sltu $11, $8, $5 ++; MIPSELR6-NEXT: selnez $9, $8, $11 ++; MIPSELR6-NEXT: seleqz $11, $5, $11 ++; MIPSELR6-NEXT: or $9, $9, $11 ++; MIPSELR6-NEXT: and $9, $9, $4 ++; MIPSELR6-NEXT: and $10, $8, $6 ++; MIPSELR6-NEXT: or $10, $10, $9 ++; MIPSELR6-NEXT: sc $10, 0($2) ++; MIPSELR6-NEXT: beqzc $10, $BB7_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: and $7, $8, $4 ++; MIPSELR6-NEXT: srlv $7, $7, $3 ++; MIPSELR6-NEXT: seh $7, $7 ++; MIPSELR6-NEXT: # %bb.3: # %entry ++; MIPSELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSELR6-NEXT: # %bb.4: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSELR6-NEXT: addiu $sp, $sp, 8 ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_umin_16: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: addiu $sp, $sp, -8 ++; MMEL-NEXT: .cfi_def_cfa_offset 8 ++; MMEL-NEXT: move $1, $5 ++; MMEL-NEXT: sync ++; MMEL-NEXT: addiu $2, $zero, -4 ++; MMEL-NEXT: and $2, $4, $2 ++; MMEL-NEXT: andi $3, $4, 3 ++; MMEL-NEXT: sll $3, $3, 3 ++; MMEL-NEXT: ori $4, $zero, 65535 ++; MMEL-NEXT: sllv $4, $4, $3 ++; MMEL-NEXT: nor $6, $zero, $4 ++; MMEL-NEXT: sllv $5, $5, $3 ++; MMEL-NEXT: $BB7_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $8, 0($2) ++; MMEL-NEXT: and $8, $8, $4 ++; MMEL-NEXT: and $5, $5, $4 ++; MMEL-NEXT: sltu $11, $8, $5 ++; MMEL-NEXT: or $9, $8, $zero ++; MMEL-NEXT: movz $9, $5, $11 ++; MMEL-NEXT: and $9, $9, $4 ++; MMEL-NEXT: and $10, $8, $6 ++; MMEL-NEXT: or $10, $10, $9 ++; MMEL-NEXT: sc $10, 0($2) ++; MMEL-NEXT: beqzc $10, $BB7_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: and $7, $8, $4 ++; MMEL-NEXT: srlv $7, $7, $3 ++; MMEL-NEXT: seh $7, $7 ++; MMEL-NEXT: # %bb.3: # %entry ++; MMEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMEL-NEXT: # %bb.4: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMEL-NEXT: addiusp 8 ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_umin_16: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: addiu $sp, $sp, -8 ++; MMELR6-NEXT: .cfi_def_cfa_offset 8 ++; MMELR6-NEXT: move $1, $5 ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: addiu $2, $zero, -4 ++; MMELR6-NEXT: and $2, $4, $2 ++; MMELR6-NEXT: andi $3, $4, 3 ++; MMELR6-NEXT: sll $3, $3, 3 ++; MMELR6-NEXT: ori $4, $zero, 65535 ++; MMELR6-NEXT: sllv $4, $4, $3 ++; MMELR6-NEXT: nor $6, $zero, $4 ++; MMELR6-NEXT: sllv $5, $5, $3 ++; MMELR6-NEXT: $BB7_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $8, 0($2) ++; MMELR6-NEXT: and $8, $8, $4 ++; MMELR6-NEXT: and $5, $5, $4 ++; MMELR6-NEXT: sltu $11, $8, $5 ++; MMELR6-NEXT: selnez $9, $8, $11 ++; MMELR6-NEXT: seleqz $11, $5, $11 ++; MMELR6-NEXT: or $9, $9, $11 ++; MMELR6-NEXT: and $9, $9, $4 ++; MMELR6-NEXT: and $10, $8, $6 ++; MMELR6-NEXT: or $10, $10, $9 ++; MMELR6-NEXT: sc $10, 0($2) ++; MMELR6-NEXT: beqc $10, $zero, $BB7_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: and $7, $8, $4 ++; MMELR6-NEXT: srlv $7, $7, $3 ++; MMELR6-NEXT: seh $7, $7 ++; MMELR6-NEXT: # %bb.3: # %entry ++; MMELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMELR6-NEXT: # %bb.4: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMELR6-NEXT: addiu $sp, $sp, 8 ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_umin_16: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: daddiu $sp, $sp, -16 ++; MIPS64-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: daddiu $1, $zero, -4 ++; MIPS64-NEXT: and $1, $4, $1 ++; MIPS64-NEXT: andi $2, $4, 3 ++; MIPS64-NEXT: xori $2, $2, 2 ++; MIPS64-NEXT: sll $2, $2, 3 ++; MIPS64-NEXT: ori $3, $zero, 65535 ++; MIPS64-NEXT: sllv $3, $3, $2 ++; MIPS64-NEXT: nor $6, $zero, $3 ++; MIPS64-NEXT: sllv $5, $5, $2 ++; MIPS64-NEXT: .LBB7_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $8, 0($1) ++; MIPS64-NEXT: sltu $11, $8, $5 ++; MIPS64-NEXT: move $9, $8 ++; MIPS64-NEXT: movz $9, $5, $11 ++; MIPS64-NEXT: and $9, $9, $3 ++; MIPS64-NEXT: and $10, $8, $6 ++; MIPS64-NEXT: or $10, $10, $9 ++; MIPS64-NEXT: sc $10, 0($1) ++; MIPS64-NEXT: beqz $10, .LBB7_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: and $7, $8, $3 ++; MIPS64-NEXT: srlv $7, $7, $2 ++; MIPS64-NEXT: seh $7, $7 ++; MIPS64-NEXT: # %bb.3: # %entry ++; MIPS64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64-NEXT: # %bb.4: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64-NEXT: daddiu $sp, $sp, 16 ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_umin_16: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64R6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: daddiu $1, $zero, -4 ++; MIPS64R6-NEXT: and $1, $4, $1 ++; MIPS64R6-NEXT: andi $2, $4, 3 ++; MIPS64R6-NEXT: xori $2, $2, 2 ++; MIPS64R6-NEXT: sll $2, $2, 3 ++; MIPS64R6-NEXT: ori $3, $zero, 65535 ++; MIPS64R6-NEXT: sllv $3, $3, $2 ++; MIPS64R6-NEXT: nor $6, $zero, $3 ++; MIPS64R6-NEXT: sllv $5, $5, $2 ++; MIPS64R6-NEXT: .LBB7_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $8, 0($1) ++; MIPS64R6-NEXT: sltu $11, $8, $5 ++; MIPS64R6-NEXT: selnez $9, $8, $11 ++; MIPS64R6-NEXT: seleqz $11, $5, $11 ++; MIPS64R6-NEXT: or $9, $9, $11 ++; MIPS64R6-NEXT: and $9, $9, $3 ++; MIPS64R6-NEXT: and $10, $8, $6 ++; MIPS64R6-NEXT: or $10, $10, $9 ++; MIPS64R6-NEXT: sc $10, 0($1) ++; MIPS64R6-NEXT: beqzc $10, .LBB7_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: and $7, $8, $3 ++; MIPS64R6-NEXT: srlv $7, $7, $2 ++; MIPS64R6-NEXT: seh $7, $7 ++; MIPS64R6-NEXT: # %bb.3: # %entry ++; MIPS64R6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64R6-NEXT: # %bb.4: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64R6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_umin_16: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: daddiu $sp, $sp, -16 ++; MIPS64EL-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: daddiu $1, $zero, -4 ++; MIPS64EL-NEXT: and $1, $4, $1 ++; MIPS64EL-NEXT: andi $2, $4, 3 ++; MIPS64EL-NEXT: sll $2, $2, 3 ++; MIPS64EL-NEXT: ori $3, $zero, 65535 ++; MIPS64EL-NEXT: sllv $3, $3, $2 ++; MIPS64EL-NEXT: nor $6, $zero, $3 ++; MIPS64EL-NEXT: sllv $5, $5, $2 ++; MIPS64EL-NEXT: .LBB7_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $8, 0($1) ++; MIPS64EL-NEXT: and $8, $8, $3 ++; MIPS64EL-NEXT: and $5, $5, $3 ++; MIPS64EL-NEXT: sltu $11, $8, $5 ++; MIPS64EL-NEXT: move $9, $8 ++; MIPS64EL-NEXT: movz $9, $5, $11 ++; MIPS64EL-NEXT: and $9, $9, $3 ++; MIPS64EL-NEXT: and $10, $8, $6 ++; MIPS64EL-NEXT: or $10, $10, $9 ++; MIPS64EL-NEXT: sc $10, 0($1) ++; MIPS64EL-NEXT: beqz $10, .LBB7_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: and $7, $8, $3 ++; MIPS64EL-NEXT: srlv $7, $7, $2 ++; MIPS64EL-NEXT: seh $7, $7 ++; MIPS64EL-NEXT: # %bb.3: # %entry ++; MIPS64EL-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64EL-NEXT: # %bb.4: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64EL-NEXT: daddiu $sp, $sp, 16 ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_umin_16: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64ELR6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: daddiu $1, $zero, -4 ++; MIPS64ELR6-NEXT: and $1, $4, $1 ++; MIPS64ELR6-NEXT: andi $2, $4, 3 ++; MIPS64ELR6-NEXT: sll $2, $2, 3 ++; MIPS64ELR6-NEXT: ori $3, $zero, 65535 ++; MIPS64ELR6-NEXT: sllv $3, $3, $2 ++; MIPS64ELR6-NEXT: nor $6, $zero, $3 ++; MIPS64ELR6-NEXT: sllv $5, $5, $2 ++; MIPS64ELR6-NEXT: .LBB7_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $8, 0($1) ++; MIPS64ELR6-NEXT: and $8, $8, $3 ++; MIPS64ELR6-NEXT: and $5, $5, $3 ++; MIPS64ELR6-NEXT: sltu $11, $8, $5 ++; MIPS64ELR6-NEXT: selnez $9, $8, $11 ++; MIPS64ELR6-NEXT: seleqz $11, $5, $11 ++; MIPS64ELR6-NEXT: or $9, $9, $11 ++; MIPS64ELR6-NEXT: and $9, $9, $3 ++; MIPS64ELR6-NEXT: and $10, $8, $6 ++; MIPS64ELR6-NEXT: or $10, $10, $9 ++; MIPS64ELR6-NEXT: sc $10, 0($1) ++; MIPS64ELR6-NEXT: beqzc $10, .LBB7_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: and $7, $8, $3 ++; MIPS64ELR6-NEXT: srlv $7, $7, $2 ++; MIPS64ELR6-NEXT: seh $7, $7 ++; MIPS64ELR6-NEXT: # %bb.3: # %entry ++; MIPS64ELR6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64ELR6-NEXT: # %bb.4: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw umin i16* %ptr, i16 %val seq_cst ++ ret i16 %0 ++} ++ ++ ++define i8 @test_max_8(i8* nocapture %ptr, i8 signext %val) { ++; MIPS-LABEL: test_max_8: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: addiu $sp, $sp, -8 ++; MIPS-NEXT: .cfi_def_cfa_offset 8 ++; MIPS-NEXT: move $1, $5 ++; MIPS-NEXT: sync ++; MIPS-NEXT: addiu $2, $zero, -4 ++; MIPS-NEXT: and $2, $4, $2 ++; MIPS-NEXT: andi $3, $4, 3 ++; MIPS-NEXT: xori $3, $3, 3 ++; MIPS-NEXT: sll $3, $3, 3 ++; MIPS-NEXT: ori $4, $zero, 255 ++; MIPS-NEXT: sllv $4, $4, $3 ++; MIPS-NEXT: nor $6, $zero, $4 ++; MIPS-NEXT: sllv $5, $5, $3 ++; MIPS-NEXT: $BB8_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $8, 0($2) ++; MIPS-NEXT: slt $11, $8, $5 ++; MIPS-NEXT: move $9, $8 ++; MIPS-NEXT: movn $9, $5, $11 ++; MIPS-NEXT: and $9, $9, $4 ++; MIPS-NEXT: and $10, $8, $6 ++; MIPS-NEXT: or $10, $10, $9 ++; MIPS-NEXT: sc $10, 0($2) ++; MIPS-NEXT: beqz $10, $BB8_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: and $7, $8, $4 ++; MIPS-NEXT: srlv $7, $7, $3 ++; MIPS-NEXT: seh $7, $7 ++; MIPS-NEXT: # %bb.3: # %entry ++; MIPS-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPS-NEXT: # %bb.4: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPS-NEXT: addiu $sp, $sp, 8 ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_max_8: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: addiu $sp, $sp, -8 ++; MIPSR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSR6-NEXT: move $1, $5 ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: addiu $2, $zero, -4 ++; MIPSR6-NEXT: and $2, $4, $2 ++; MIPSR6-NEXT: andi $3, $4, 3 ++; MIPSR6-NEXT: xori $3, $3, 3 ++; MIPSR6-NEXT: sll $3, $3, 3 ++; MIPSR6-NEXT: ori $4, $zero, 255 ++; MIPSR6-NEXT: sllv $4, $4, $3 ++; MIPSR6-NEXT: nor $6, $zero, $4 ++; MIPSR6-NEXT: sllv $5, $5, $3 ++; MIPSR6-NEXT: $BB8_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $8, 0($2) ++; MIPSR6-NEXT: slt $11, $8, $5 ++; MIPSR6-NEXT: seleqz $9, $8, $11 ++; MIPSR6-NEXT: selnez $11, $5, $11 ++; MIPSR6-NEXT: or $9, $9, $11 ++; MIPSR6-NEXT: and $9, $9, $4 ++; MIPSR6-NEXT: and $10, $8, $6 ++; MIPSR6-NEXT: or $10, $10, $9 ++; MIPSR6-NEXT: sc $10, 0($2) ++; MIPSR6-NEXT: beqzc $10, $BB8_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: and $7, $8, $4 ++; MIPSR6-NEXT: srlv $7, $7, $3 ++; MIPSR6-NEXT: seh $7, $7 ++; MIPSR6-NEXT: # %bb.3: # %entry ++; MIPSR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSR6-NEXT: # %bb.4: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSR6-NEXT: addiu $sp, $sp, 8 ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_max_8: ++; MM: # %bb.0: # %entry ++; MM-NEXT: addiu $sp, $sp, -8 ++; MM-NEXT: .cfi_def_cfa_offset 8 ++; MM-NEXT: move $1, $5 ++; MM-NEXT: sync ++; MM-NEXT: addiu $2, $zero, -4 ++; MM-NEXT: and $2, $4, $2 ++; MM-NEXT: andi $3, $4, 3 ++; MM-NEXT: xori $3, $3, 3 ++; MM-NEXT: sll $3, $3, 3 ++; MM-NEXT: ori $4, $zero, 255 ++; MM-NEXT: sllv $4, $4, $3 ++; MM-NEXT: nor $6, $zero, $4 ++; MM-NEXT: sllv $5, $5, $3 ++; MM-NEXT: $BB8_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $8, 0($2) ++; MM-NEXT: slt $11, $8, $5 ++; MM-NEXT: or $9, $8, $zero ++; MM-NEXT: movn $9, $5, $11 ++; MM-NEXT: and $9, $9, $4 ++; MM-NEXT: and $10, $8, $6 ++; MM-NEXT: or $10, $10, $9 ++; MM-NEXT: sc $10, 0($2) ++; MM-NEXT: beqzc $10, $BB8_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: and $7, $8, $4 ++; MM-NEXT: srlv $7, $7, $3 ++; MM-NEXT: seh $7, $7 ++; MM-NEXT: # %bb.3: # %entry ++; MM-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MM-NEXT: # %bb.4: # %entry ++; MM-NEXT: sync ++; MM-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MM-NEXT: addiusp 8 ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_max_8: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: addiu $sp, $sp, -8 ++; MMR6-NEXT: .cfi_def_cfa_offset 8 ++; MMR6-NEXT: move $1, $5 ++; MMR6-NEXT: sync ++; MMR6-NEXT: addiu $2, $zero, -4 ++; MMR6-NEXT: and $2, $4, $2 ++; MMR6-NEXT: andi $3, $4, 3 ++; MMR6-NEXT: xori $3, $3, 3 ++; MMR6-NEXT: sll $3, $3, 3 ++; MMR6-NEXT: ori $4, $zero, 255 ++; MMR6-NEXT: sllv $4, $4, $3 ++; MMR6-NEXT: nor $6, $zero, $4 ++; MMR6-NEXT: sllv $5, $5, $3 ++; MMR6-NEXT: $BB8_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $8, 0($2) ++; MMR6-NEXT: slt $11, $8, $5 ++; MMR6-NEXT: seleqz $9, $8, $11 ++; MMR6-NEXT: selnez $11, $5, $11 ++; MMR6-NEXT: or $9, $9, $11 ++; MMR6-NEXT: and $9, $9, $4 ++; MMR6-NEXT: and $10, $8, $6 ++; MMR6-NEXT: or $10, $10, $9 ++; MMR6-NEXT: sc $10, 0($2) ++; MMR6-NEXT: beqc $10, $zero, $BB8_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: and $7, $8, $4 ++; MMR6-NEXT: srlv $7, $7, $3 ++; MMR6-NEXT: seh $7, $7 ++; MMR6-NEXT: # %bb.3: # %entry ++; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMR6-NEXT: # %bb.4: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMR6-NEXT: addiu $sp, $sp, 8 ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_max_8: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: addiu $sp, $sp, -8 ++; MIPSEL-NEXT: .cfi_def_cfa_offset 8 ++; MIPSEL-NEXT: move $1, $5 ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: addiu $2, $zero, -4 ++; MIPSEL-NEXT: and $2, $4, $2 ++; MIPSEL-NEXT: andi $3, $4, 3 ++; MIPSEL-NEXT: sll $3, $3, 3 ++; MIPSEL-NEXT: ori $4, $zero, 255 ++; MIPSEL-NEXT: sllv $4, $4, $3 ++; MIPSEL-NEXT: nor $6, $zero, $4 ++; MIPSEL-NEXT: sllv $5, $5, $3 ++; MIPSEL-NEXT: $BB8_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $8, 0($2) ++; MIPSEL-NEXT: and $8, $8, $4 ++; MIPSEL-NEXT: and $5, $5, $4 ++; MIPSEL-NEXT: slt $11, $8, $5 ++; MIPSEL-NEXT: move $9, $8 ++; MIPSEL-NEXT: movn $9, $5, $11 ++; MIPSEL-NEXT: and $9, $9, $4 ++; MIPSEL-NEXT: and $10, $8, $6 ++; MIPSEL-NEXT: or $10, $10, $9 ++; MIPSEL-NEXT: sc $10, 0($2) ++; MIPSEL-NEXT: beqz $10, $BB8_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: and $7, $8, $4 ++; MIPSEL-NEXT: srlv $7, $7, $3 ++; MIPSEL-NEXT: seh $7, $7 ++; MIPSEL-NEXT: # %bb.3: # %entry ++; MIPSEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSEL-NEXT: # %bb.4: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSEL-NEXT: addiu $sp, $sp, 8 ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_max_8: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: addiu $sp, $sp, -8 ++; MIPSELR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSELR6-NEXT: move $1, $5 ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: addiu $2, $zero, -4 ++; MIPSELR6-NEXT: and $2, $4, $2 ++; MIPSELR6-NEXT: andi $3, $4, 3 ++; MIPSELR6-NEXT: sll $3, $3, 3 ++; MIPSELR6-NEXT: ori $4, $zero, 255 ++; MIPSELR6-NEXT: sllv $4, $4, $3 ++; MIPSELR6-NEXT: nor $6, $zero, $4 ++; MIPSELR6-NEXT: sllv $5, $5, $3 ++; MIPSELR6-NEXT: $BB8_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $8, 0($2) ++; MIPSELR6-NEXT: and $8, $8, $4 ++; MIPSELR6-NEXT: and $5, $5, $4 ++; MIPSELR6-NEXT: slt $11, $8, $5 ++; MIPSELR6-NEXT: seleqz $9, $8, $11 ++; MIPSELR6-NEXT: selnez $11, $5, $11 ++; MIPSELR6-NEXT: or $9, $9, $11 ++; MIPSELR6-NEXT: and $9, $9, $4 ++; MIPSELR6-NEXT: and $10, $8, $6 ++; MIPSELR6-NEXT: or $10, $10, $9 ++; MIPSELR6-NEXT: sc $10, 0($2) ++; MIPSELR6-NEXT: beqzc $10, $BB8_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: and $7, $8, $4 ++; MIPSELR6-NEXT: srlv $7, $7, $3 ++; MIPSELR6-NEXT: seh $7, $7 ++; MIPSELR6-NEXT: # %bb.3: # %entry ++; MIPSELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSELR6-NEXT: # %bb.4: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSELR6-NEXT: addiu $sp, $sp, 8 ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_max_8: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: addiu $sp, $sp, -8 ++; MMEL-NEXT: .cfi_def_cfa_offset 8 ++; MMEL-NEXT: move $1, $5 ++; MMEL-NEXT: sync ++; MMEL-NEXT: addiu $2, $zero, -4 ++; MMEL-NEXT: and $2, $4, $2 ++; MMEL-NEXT: andi $3, $4, 3 ++; MMEL-NEXT: sll $3, $3, 3 ++; MMEL-NEXT: ori $4, $zero, 255 ++; MMEL-NEXT: sllv $4, $4, $3 ++; MMEL-NEXT: nor $6, $zero, $4 ++; MMEL-NEXT: sllv $5, $5, $3 ++; MMEL-NEXT: $BB8_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $8, 0($2) ++; MMEL-NEXT: and $8, $8, $4 ++; MMEL-NEXT: and $5, $5, $4 ++; MMEL-NEXT: slt $11, $8, $5 ++; MMEL-NEXT: or $9, $8, $zero ++; MMEL-NEXT: movn $9, $5, $11 ++; MMEL-NEXT: and $9, $9, $4 ++; MMEL-NEXT: and $10, $8, $6 ++; MMEL-NEXT: or $10, $10, $9 ++; MMEL-NEXT: sc $10, 0($2) ++; MMEL-NEXT: beqzc $10, $BB8_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: and $7, $8, $4 ++; MMEL-NEXT: srlv $7, $7, $3 ++; MMEL-NEXT: seh $7, $7 ++; MMEL-NEXT: # %bb.3: # %entry ++; MMEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMEL-NEXT: # %bb.4: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMEL-NEXT: addiusp 8 ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_max_8: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: addiu $sp, $sp, -8 ++; MMELR6-NEXT: .cfi_def_cfa_offset 8 ++; MMELR6-NEXT: move $1, $5 ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: addiu $2, $zero, -4 ++; MMELR6-NEXT: and $2, $4, $2 ++; MMELR6-NEXT: andi $3, $4, 3 ++; MMELR6-NEXT: sll $3, $3, 3 ++; MMELR6-NEXT: ori $4, $zero, 255 ++; MMELR6-NEXT: sllv $4, $4, $3 ++; MMELR6-NEXT: nor $6, $zero, $4 ++; MMELR6-NEXT: sllv $5, $5, $3 ++; MMELR6-NEXT: $BB8_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $8, 0($2) ++; MMELR6-NEXT: and $8, $8, $4 ++; MMELR6-NEXT: and $5, $5, $4 ++; MMELR6-NEXT: slt $11, $8, $5 ++; MMELR6-NEXT: seleqz $9, $8, $11 ++; MMELR6-NEXT: selnez $11, $5, $11 ++; MMELR6-NEXT: or $9, $9, $11 ++; MMELR6-NEXT: and $9, $9, $4 ++; MMELR6-NEXT: and $10, $8, $6 ++; MMELR6-NEXT: or $10, $10, $9 ++; MMELR6-NEXT: sc $10, 0($2) ++; MMELR6-NEXT: beqc $10, $zero, $BB8_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: and $7, $8, $4 ++; MMELR6-NEXT: srlv $7, $7, $3 ++; MMELR6-NEXT: seh $7, $7 ++; MMELR6-NEXT: # %bb.3: # %entry ++; MMELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMELR6-NEXT: # %bb.4: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMELR6-NEXT: addiu $sp, $sp, 8 ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_max_8: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: daddiu $sp, $sp, -16 ++; MIPS64-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: daddiu $1, $zero, -4 ++; MIPS64-NEXT: and $1, $4, $1 ++; MIPS64-NEXT: andi $2, $4, 3 ++; MIPS64-NEXT: xori $2, $2, 3 ++; MIPS64-NEXT: sll $2, $2, 3 ++; MIPS64-NEXT: ori $3, $zero, 255 ++; MIPS64-NEXT: sllv $3, $3, $2 ++; MIPS64-NEXT: nor $6, $zero, $3 ++; MIPS64-NEXT: sllv $5, $5, $2 ++; MIPS64-NEXT: .LBB8_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $8, 0($1) ++; MIPS64-NEXT: slt $11, $8, $5 ++; MIPS64-NEXT: move $9, $8 ++; MIPS64-NEXT: movn $9, $5, $11 ++; MIPS64-NEXT: and $9, $9, $3 ++; MIPS64-NEXT: and $10, $8, $6 ++; MIPS64-NEXT: or $10, $10, $9 ++; MIPS64-NEXT: sc $10, 0($1) ++; MIPS64-NEXT: beqz $10, .LBB8_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: and $7, $8, $3 ++; MIPS64-NEXT: srlv $7, $7, $2 ++; MIPS64-NEXT: seh $7, $7 ++; MIPS64-NEXT: # %bb.3: # %entry ++; MIPS64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64-NEXT: # %bb.4: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64-NEXT: daddiu $sp, $sp, 16 ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_max_8: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64R6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: daddiu $1, $zero, -4 ++; MIPS64R6-NEXT: and $1, $4, $1 ++; MIPS64R6-NEXT: andi $2, $4, 3 ++; MIPS64R6-NEXT: xori $2, $2, 3 ++; MIPS64R6-NEXT: sll $2, $2, 3 ++; MIPS64R6-NEXT: ori $3, $zero, 255 ++; MIPS64R6-NEXT: sllv $3, $3, $2 ++; MIPS64R6-NEXT: nor $6, $zero, $3 ++; MIPS64R6-NEXT: sllv $5, $5, $2 ++; MIPS64R6-NEXT: .LBB8_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $8, 0($1) ++; MIPS64R6-NEXT: slt $11, $8, $5 ++; MIPS64R6-NEXT: seleqz $9, $8, $11 ++; MIPS64R6-NEXT: selnez $11, $5, $11 ++; MIPS64R6-NEXT: or $9, $9, $11 ++; MIPS64R6-NEXT: and $9, $9, $3 ++; MIPS64R6-NEXT: and $10, $8, $6 ++; MIPS64R6-NEXT: or $10, $10, $9 ++; MIPS64R6-NEXT: sc $10, 0($1) ++; MIPS64R6-NEXT: beqzc $10, .LBB8_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: and $7, $8, $3 ++; MIPS64R6-NEXT: srlv $7, $7, $2 ++; MIPS64R6-NEXT: seh $7, $7 ++; MIPS64R6-NEXT: # %bb.3: # %entry ++; MIPS64R6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64R6-NEXT: # %bb.4: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64R6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_max_8: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: daddiu $sp, $sp, -16 ++; MIPS64EL-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: daddiu $1, $zero, -4 ++; MIPS64EL-NEXT: and $1, $4, $1 ++; MIPS64EL-NEXT: andi $2, $4, 3 ++; MIPS64EL-NEXT: sll $2, $2, 3 ++; MIPS64EL-NEXT: ori $3, $zero, 255 ++; MIPS64EL-NEXT: sllv $3, $3, $2 ++; MIPS64EL-NEXT: nor $6, $zero, $3 ++; MIPS64EL-NEXT: sllv $5, $5, $2 ++; MIPS64EL-NEXT: .LBB8_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $8, 0($1) ++; MIPS64EL-NEXT: and $8, $8, $3 ++; MIPS64EL-NEXT: and $5, $5, $3 ++; MIPS64EL-NEXT: slt $11, $8, $5 ++; MIPS64EL-NEXT: move $9, $8 ++; MIPS64EL-NEXT: movn $9, $5, $11 ++; MIPS64EL-NEXT: and $9, $9, $3 ++; MIPS64EL-NEXT: and $10, $8, $6 ++; MIPS64EL-NEXT: or $10, $10, $9 ++; MIPS64EL-NEXT: sc $10, 0($1) ++; MIPS64EL-NEXT: beqz $10, .LBB8_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: and $7, $8, $3 ++; MIPS64EL-NEXT: srlv $7, $7, $2 ++; MIPS64EL-NEXT: seh $7, $7 ++; MIPS64EL-NEXT: # %bb.3: # %entry ++; MIPS64EL-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64EL-NEXT: # %bb.4: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64EL-NEXT: daddiu $sp, $sp, 16 ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_max_8: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64ELR6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: daddiu $1, $zero, -4 ++; MIPS64ELR6-NEXT: and $1, $4, $1 ++; MIPS64ELR6-NEXT: andi $2, $4, 3 ++; MIPS64ELR6-NEXT: sll $2, $2, 3 ++; MIPS64ELR6-NEXT: ori $3, $zero, 255 ++; MIPS64ELR6-NEXT: sllv $3, $3, $2 ++; MIPS64ELR6-NEXT: nor $6, $zero, $3 ++; MIPS64ELR6-NEXT: sllv $5, $5, $2 ++; MIPS64ELR6-NEXT: .LBB8_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $8, 0($1) ++; MIPS64ELR6-NEXT: and $8, $8, $3 ++; MIPS64ELR6-NEXT: and $5, $5, $3 ++; MIPS64ELR6-NEXT: slt $11, $8, $5 ++; MIPS64ELR6-NEXT: seleqz $9, $8, $11 ++; MIPS64ELR6-NEXT: selnez $11, $5, $11 ++; MIPS64ELR6-NEXT: or $9, $9, $11 ++; MIPS64ELR6-NEXT: and $9, $9, $3 ++; MIPS64ELR6-NEXT: and $10, $8, $6 ++; MIPS64ELR6-NEXT: or $10, $10, $9 ++; MIPS64ELR6-NEXT: sc $10, 0($1) ++; MIPS64ELR6-NEXT: beqzc $10, .LBB8_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: and $7, $8, $3 ++; MIPS64ELR6-NEXT: srlv $7, $7, $2 ++; MIPS64ELR6-NEXT: seh $7, $7 ++; MIPS64ELR6-NEXT: # %bb.3: # %entry ++; MIPS64ELR6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64ELR6-NEXT: # %bb.4: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw max i8* %ptr, i8 %val seq_cst ++ ret i8 %0 ++} ++ ++define i8 @test_min_8(i8* nocapture %ptr, i8 signext %val) { ++; MIPS-LABEL: test_min_8: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: addiu $sp, $sp, -8 ++; MIPS-NEXT: .cfi_def_cfa_offset 8 ++; MIPS-NEXT: move $1, $5 ++; MIPS-NEXT: sync ++; MIPS-NEXT: addiu $2, $zero, -4 ++; MIPS-NEXT: and $2, $4, $2 ++; MIPS-NEXT: andi $3, $4, 3 ++; MIPS-NEXT: xori $3, $3, 3 ++; MIPS-NEXT: sll $3, $3, 3 ++; MIPS-NEXT: ori $4, $zero, 255 ++; MIPS-NEXT: sllv $4, $4, $3 ++; MIPS-NEXT: nor $6, $zero, $4 ++; MIPS-NEXT: sllv $5, $5, $3 ++; MIPS-NEXT: $BB9_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $8, 0($2) ++; MIPS-NEXT: slt $11, $8, $5 ++; MIPS-NEXT: move $9, $8 ++; MIPS-NEXT: movz $9, $5, $11 ++; MIPS-NEXT: and $9, $9, $4 ++; MIPS-NEXT: and $10, $8, $6 ++; MIPS-NEXT: or $10, $10, $9 ++; MIPS-NEXT: sc $10, 0($2) ++; MIPS-NEXT: beqz $10, $BB9_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: and $7, $8, $4 ++; MIPS-NEXT: srlv $7, $7, $3 ++; MIPS-NEXT: seh $7, $7 ++; MIPS-NEXT: # %bb.3: # %entry ++; MIPS-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPS-NEXT: # %bb.4: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPS-NEXT: addiu $sp, $sp, 8 ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_min_8: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: addiu $sp, $sp, -8 ++; MIPSR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSR6-NEXT: move $1, $5 ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: addiu $2, $zero, -4 ++; MIPSR6-NEXT: and $2, $4, $2 ++; MIPSR6-NEXT: andi $3, $4, 3 ++; MIPSR6-NEXT: xori $3, $3, 3 ++; MIPSR6-NEXT: sll $3, $3, 3 ++; MIPSR6-NEXT: ori $4, $zero, 255 ++; MIPSR6-NEXT: sllv $4, $4, $3 ++; MIPSR6-NEXT: nor $6, $zero, $4 ++; MIPSR6-NEXT: sllv $5, $5, $3 ++; MIPSR6-NEXT: $BB9_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $8, 0($2) ++; MIPSR6-NEXT: slt $11, $8, $5 ++; MIPSR6-NEXT: selnez $9, $8, $11 ++; MIPSR6-NEXT: seleqz $11, $5, $11 ++; MIPSR6-NEXT: or $9, $9, $11 ++; MIPSR6-NEXT: and $9, $9, $4 ++; MIPSR6-NEXT: and $10, $8, $6 ++; MIPSR6-NEXT: or $10, $10, $9 ++; MIPSR6-NEXT: sc $10, 0($2) ++; MIPSR6-NEXT: beqzc $10, $BB9_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: and $7, $8, $4 ++; MIPSR6-NEXT: srlv $7, $7, $3 ++; MIPSR6-NEXT: seh $7, $7 ++; MIPSR6-NEXT: # %bb.3: # %entry ++; MIPSR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSR6-NEXT: # %bb.4: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSR6-NEXT: addiu $sp, $sp, 8 ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_min_8: ++; MM: # %bb.0: # %entry ++; MM-NEXT: addiu $sp, $sp, -8 ++; MM-NEXT: .cfi_def_cfa_offset 8 ++; MM-NEXT: move $1, $5 ++; MM-NEXT: sync ++; MM-NEXT: addiu $2, $zero, -4 ++; MM-NEXT: and $2, $4, $2 ++; MM-NEXT: andi $3, $4, 3 ++; MM-NEXT: xori $3, $3, 3 ++; MM-NEXT: sll $3, $3, 3 ++; MM-NEXT: ori $4, $zero, 255 ++; MM-NEXT: sllv $4, $4, $3 ++; MM-NEXT: nor $6, $zero, $4 ++; MM-NEXT: sllv $5, $5, $3 ++; MM-NEXT: $BB9_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $8, 0($2) ++; MM-NEXT: slt $11, $8, $5 ++; MM-NEXT: or $9, $8, $zero ++; MM-NEXT: movz $9, $5, $11 ++; MM-NEXT: and $9, $9, $4 ++; MM-NEXT: and $10, $8, $6 ++; MM-NEXT: or $10, $10, $9 ++; MM-NEXT: sc $10, 0($2) ++; MM-NEXT: beqzc $10, $BB9_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: and $7, $8, $4 ++; MM-NEXT: srlv $7, $7, $3 ++; MM-NEXT: seh $7, $7 ++; MM-NEXT: # %bb.3: # %entry ++; MM-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MM-NEXT: # %bb.4: # %entry ++; MM-NEXT: sync ++; MM-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MM-NEXT: addiusp 8 ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_min_8: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: addiu $sp, $sp, -8 ++; MMR6-NEXT: .cfi_def_cfa_offset 8 ++; MMR6-NEXT: move $1, $5 ++; MMR6-NEXT: sync ++; MMR6-NEXT: addiu $2, $zero, -4 ++; MMR6-NEXT: and $2, $4, $2 ++; MMR6-NEXT: andi $3, $4, 3 ++; MMR6-NEXT: xori $3, $3, 3 ++; MMR6-NEXT: sll $3, $3, 3 ++; MMR6-NEXT: ori $4, $zero, 255 ++; MMR6-NEXT: sllv $4, $4, $3 ++; MMR6-NEXT: nor $6, $zero, $4 ++; MMR6-NEXT: sllv $5, $5, $3 ++; MMR6-NEXT: $BB9_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $8, 0($2) ++; MMR6-NEXT: slt $11, $8, $5 ++; MMR6-NEXT: selnez $9, $8, $11 ++; MMR6-NEXT: seleqz $11, $5, $11 ++; MMR6-NEXT: or $9, $9, $11 ++; MMR6-NEXT: and $9, $9, $4 ++; MMR6-NEXT: and $10, $8, $6 ++; MMR6-NEXT: or $10, $10, $9 ++; MMR6-NEXT: sc $10, 0($2) ++; MMR6-NEXT: beqc $10, $zero, $BB9_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: and $7, $8, $4 ++; MMR6-NEXT: srlv $7, $7, $3 ++; MMR6-NEXT: seh $7, $7 ++; MMR6-NEXT: # %bb.3: # %entry ++; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMR6-NEXT: # %bb.4: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMR6-NEXT: addiu $sp, $sp, 8 ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_min_8: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: addiu $sp, $sp, -8 ++; MIPSEL-NEXT: .cfi_def_cfa_offset 8 ++; MIPSEL-NEXT: move $1, $5 ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: addiu $2, $zero, -4 ++; MIPSEL-NEXT: and $2, $4, $2 ++; MIPSEL-NEXT: andi $3, $4, 3 ++; MIPSEL-NEXT: sll $3, $3, 3 ++; MIPSEL-NEXT: ori $4, $zero, 255 ++; MIPSEL-NEXT: sllv $4, $4, $3 ++; MIPSEL-NEXT: nor $6, $zero, $4 ++; MIPSEL-NEXT: sllv $5, $5, $3 ++; MIPSEL-NEXT: $BB9_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $8, 0($2) ++; MIPSEL-NEXT: and $8, $8, $4 ++; MIPSEL-NEXT: and $5, $5, $4 ++; MIPSEL-NEXT: slt $11, $8, $5 ++; MIPSEL-NEXT: move $9, $8 ++; MIPSEL-NEXT: movz $9, $5, $11 ++; MIPSEL-NEXT: and $9, $9, $4 ++; MIPSEL-NEXT: and $10, $8, $6 ++; MIPSEL-NEXT: or $10, $10, $9 ++; MIPSEL-NEXT: sc $10, 0($2) ++; MIPSEL-NEXT: beqz $10, $BB9_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: and $7, $8, $4 ++; MIPSEL-NEXT: srlv $7, $7, $3 ++; MIPSEL-NEXT: seh $7, $7 ++; MIPSEL-NEXT: # %bb.3: # %entry ++; MIPSEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSEL-NEXT: # %bb.4: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSEL-NEXT: addiu $sp, $sp, 8 ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_min_8: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: addiu $sp, $sp, -8 ++; MIPSELR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSELR6-NEXT: move $1, $5 ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: addiu $2, $zero, -4 ++; MIPSELR6-NEXT: and $2, $4, $2 ++; MIPSELR6-NEXT: andi $3, $4, 3 ++; MIPSELR6-NEXT: sll $3, $3, 3 ++; MIPSELR6-NEXT: ori $4, $zero, 255 ++; MIPSELR6-NEXT: sllv $4, $4, $3 ++; MIPSELR6-NEXT: nor $6, $zero, $4 ++; MIPSELR6-NEXT: sllv $5, $5, $3 ++; MIPSELR6-NEXT: $BB9_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $8, 0($2) ++; MIPSELR6-NEXT: and $8, $8, $4 ++; MIPSELR6-NEXT: and $5, $5, $4 ++; MIPSELR6-NEXT: slt $11, $8, $5 ++; MIPSELR6-NEXT: selnez $9, $8, $11 ++; MIPSELR6-NEXT: seleqz $11, $5, $11 ++; MIPSELR6-NEXT: or $9, $9, $11 ++; MIPSELR6-NEXT: and $9, $9, $4 ++; MIPSELR6-NEXT: and $10, $8, $6 ++; MIPSELR6-NEXT: or $10, $10, $9 ++; MIPSELR6-NEXT: sc $10, 0($2) ++; MIPSELR6-NEXT: beqzc $10, $BB9_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: and $7, $8, $4 ++; MIPSELR6-NEXT: srlv $7, $7, $3 ++; MIPSELR6-NEXT: seh $7, $7 ++; MIPSELR6-NEXT: # %bb.3: # %entry ++; MIPSELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSELR6-NEXT: # %bb.4: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSELR6-NEXT: addiu $sp, $sp, 8 ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_min_8: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: addiu $sp, $sp, -8 ++; MMEL-NEXT: .cfi_def_cfa_offset 8 ++; MMEL-NEXT: move $1, $5 ++; MMEL-NEXT: sync ++; MMEL-NEXT: addiu $2, $zero, -4 ++; MMEL-NEXT: and $2, $4, $2 ++; MMEL-NEXT: andi $3, $4, 3 ++; MMEL-NEXT: sll $3, $3, 3 ++; MMEL-NEXT: ori $4, $zero, 255 ++; MMEL-NEXT: sllv $4, $4, $3 ++; MMEL-NEXT: nor $6, $zero, $4 ++; MMEL-NEXT: sllv $5, $5, $3 ++; MMEL-NEXT: $BB9_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $8, 0($2) ++; MMEL-NEXT: and $8, $8, $4 ++; MMEL-NEXT: and $5, $5, $4 ++; MMEL-NEXT: slt $11, $8, $5 ++; MMEL-NEXT: or $9, $8, $zero ++; MMEL-NEXT: movz $9, $5, $11 ++; MMEL-NEXT: and $9, $9, $4 ++; MMEL-NEXT: and $10, $8, $6 ++; MMEL-NEXT: or $10, $10, $9 ++; MMEL-NEXT: sc $10, 0($2) ++; MMEL-NEXT: beqzc $10, $BB9_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: and $7, $8, $4 ++; MMEL-NEXT: srlv $7, $7, $3 ++; MMEL-NEXT: seh $7, $7 ++; MMEL-NEXT: # %bb.3: # %entry ++; MMEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMEL-NEXT: # %bb.4: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMEL-NEXT: addiusp 8 ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_min_8: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: addiu $sp, $sp, -8 ++; MMELR6-NEXT: .cfi_def_cfa_offset 8 ++; MMELR6-NEXT: move $1, $5 ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: addiu $2, $zero, -4 ++; MMELR6-NEXT: and $2, $4, $2 ++; MMELR6-NEXT: andi $3, $4, 3 ++; MMELR6-NEXT: sll $3, $3, 3 ++; MMELR6-NEXT: ori $4, $zero, 255 ++; MMELR6-NEXT: sllv $4, $4, $3 ++; MMELR6-NEXT: nor $6, $zero, $4 ++; MMELR6-NEXT: sllv $5, $5, $3 ++; MMELR6-NEXT: $BB9_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $8, 0($2) ++; MMELR6-NEXT: and $8, $8, $4 ++; MMELR6-NEXT: and $5, $5, $4 ++; MMELR6-NEXT: slt $11, $8, $5 ++; MMELR6-NEXT: selnez $9, $8, $11 ++; MMELR6-NEXT: seleqz $11, $5, $11 ++; MMELR6-NEXT: or $9, $9, $11 ++; MMELR6-NEXT: and $9, $9, $4 ++; MMELR6-NEXT: and $10, $8, $6 ++; MMELR6-NEXT: or $10, $10, $9 ++; MMELR6-NEXT: sc $10, 0($2) ++; MMELR6-NEXT: beqc $10, $zero, $BB9_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: and $7, $8, $4 ++; MMELR6-NEXT: srlv $7, $7, $3 ++; MMELR6-NEXT: seh $7, $7 ++; MMELR6-NEXT: # %bb.3: # %entry ++; MMELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMELR6-NEXT: # %bb.4: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMELR6-NEXT: addiu $sp, $sp, 8 ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_min_8: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: daddiu $sp, $sp, -16 ++; MIPS64-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: daddiu $1, $zero, -4 ++; MIPS64-NEXT: and $1, $4, $1 ++; MIPS64-NEXT: andi $2, $4, 3 ++; MIPS64-NEXT: xori $2, $2, 3 ++; MIPS64-NEXT: sll $2, $2, 3 ++; MIPS64-NEXT: ori $3, $zero, 255 ++; MIPS64-NEXT: sllv $3, $3, $2 ++; MIPS64-NEXT: nor $6, $zero, $3 ++; MIPS64-NEXT: sllv $5, $5, $2 ++; MIPS64-NEXT: .LBB9_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $8, 0($1) ++; MIPS64-NEXT: slt $11, $8, $5 ++; MIPS64-NEXT: move $9, $8 ++; MIPS64-NEXT: movz $9, $5, $11 ++; MIPS64-NEXT: and $9, $9, $3 ++; MIPS64-NEXT: and $10, $8, $6 ++; MIPS64-NEXT: or $10, $10, $9 ++; MIPS64-NEXT: sc $10, 0($1) ++; MIPS64-NEXT: beqz $10, .LBB9_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: and $7, $8, $3 ++; MIPS64-NEXT: srlv $7, $7, $2 ++; MIPS64-NEXT: seh $7, $7 ++; MIPS64-NEXT: # %bb.3: # %entry ++; MIPS64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64-NEXT: # %bb.4: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64-NEXT: daddiu $sp, $sp, 16 ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_min_8: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64R6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: daddiu $1, $zero, -4 ++; MIPS64R6-NEXT: and $1, $4, $1 ++; MIPS64R6-NEXT: andi $2, $4, 3 ++; MIPS64R6-NEXT: xori $2, $2, 3 ++; MIPS64R6-NEXT: sll $2, $2, 3 ++; MIPS64R6-NEXT: ori $3, $zero, 255 ++; MIPS64R6-NEXT: sllv $3, $3, $2 ++; MIPS64R6-NEXT: nor $6, $zero, $3 ++; MIPS64R6-NEXT: sllv $5, $5, $2 ++; MIPS64R6-NEXT: .LBB9_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $8, 0($1) ++; MIPS64R6-NEXT: slt $11, $8, $5 ++; MIPS64R6-NEXT: selnez $9, $8, $11 ++; MIPS64R6-NEXT: seleqz $11, $5, $11 ++; MIPS64R6-NEXT: or $9, $9, $11 ++; MIPS64R6-NEXT: and $9, $9, $3 ++; MIPS64R6-NEXT: and $10, $8, $6 ++; MIPS64R6-NEXT: or $10, $10, $9 ++; MIPS64R6-NEXT: sc $10, 0($1) ++; MIPS64R6-NEXT: beqzc $10, .LBB9_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: and $7, $8, $3 ++; MIPS64R6-NEXT: srlv $7, $7, $2 ++; MIPS64R6-NEXT: seh $7, $7 ++; MIPS64R6-NEXT: # %bb.3: # %entry ++; MIPS64R6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64R6-NEXT: # %bb.4: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64R6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_min_8: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: daddiu $sp, $sp, -16 ++; MIPS64EL-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: daddiu $1, $zero, -4 ++; MIPS64EL-NEXT: and $1, $4, $1 ++; MIPS64EL-NEXT: andi $2, $4, 3 ++; MIPS64EL-NEXT: sll $2, $2, 3 ++; MIPS64EL-NEXT: ori $3, $zero, 255 ++; MIPS64EL-NEXT: sllv $3, $3, $2 ++; MIPS64EL-NEXT: nor $6, $zero, $3 ++; MIPS64EL-NEXT: sllv $5, $5, $2 ++; MIPS64EL-NEXT: .LBB9_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $8, 0($1) ++; MIPS64EL-NEXT: and $8, $8, $3 ++; MIPS64EL-NEXT: and $5, $5, $3 ++; MIPS64EL-NEXT: slt $11, $8, $5 ++; MIPS64EL-NEXT: move $9, $8 ++; MIPS64EL-NEXT: movz $9, $5, $11 ++; MIPS64EL-NEXT: and $9, $9, $3 ++; MIPS64EL-NEXT: and $10, $8, $6 ++; MIPS64EL-NEXT: or $10, $10, $9 ++; MIPS64EL-NEXT: sc $10, 0($1) ++; MIPS64EL-NEXT: beqz $10, .LBB9_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: and $7, $8, $3 ++; MIPS64EL-NEXT: srlv $7, $7, $2 ++; MIPS64EL-NEXT: seh $7, $7 ++; MIPS64EL-NEXT: # %bb.3: # %entry ++; MIPS64EL-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64EL-NEXT: # %bb.4: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64EL-NEXT: daddiu $sp, $sp, 16 ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_min_8: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64ELR6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: daddiu $1, $zero, -4 ++; MIPS64ELR6-NEXT: and $1, $4, $1 ++; MIPS64ELR6-NEXT: andi $2, $4, 3 ++; MIPS64ELR6-NEXT: sll $2, $2, 3 ++; MIPS64ELR6-NEXT: ori $3, $zero, 255 ++; MIPS64ELR6-NEXT: sllv $3, $3, $2 ++; MIPS64ELR6-NEXT: nor $6, $zero, $3 ++; MIPS64ELR6-NEXT: sllv $5, $5, $2 ++; MIPS64ELR6-NEXT: .LBB9_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $8, 0($1) ++; MIPS64ELR6-NEXT: and $8, $8, $3 ++; MIPS64ELR6-NEXT: and $5, $5, $3 ++; MIPS64ELR6-NEXT: slt $11, $8, $5 ++; MIPS64ELR6-NEXT: selnez $9, $8, $11 ++; MIPS64ELR6-NEXT: seleqz $11, $5, $11 ++; MIPS64ELR6-NEXT: or $9, $9, $11 ++; MIPS64ELR6-NEXT: and $9, $9, $3 ++; MIPS64ELR6-NEXT: and $10, $8, $6 ++; MIPS64ELR6-NEXT: or $10, $10, $9 ++; MIPS64ELR6-NEXT: sc $10, 0($1) ++; MIPS64ELR6-NEXT: beqzc $10, .LBB9_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: and $7, $8, $3 ++; MIPS64ELR6-NEXT: srlv $7, $7, $2 ++; MIPS64ELR6-NEXT: seh $7, $7 ++; MIPS64ELR6-NEXT: # %bb.3: # %entry ++; MIPS64ELR6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64ELR6-NEXT: # %bb.4: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw min i8* %ptr, i8 %val seq_cst ++ ret i8 %0 ++} ++ ++define i8 @test_umax_8(i8* nocapture %ptr, i8 signext %val) { ++; MIPS-LABEL: test_umax_8: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: addiu $sp, $sp, -8 ++; MIPS-NEXT: .cfi_def_cfa_offset 8 ++; MIPS-NEXT: move $1, $5 ++; MIPS-NEXT: sync ++; MIPS-NEXT: addiu $2, $zero, -4 ++; MIPS-NEXT: and $2, $4, $2 ++; MIPS-NEXT: andi $3, $4, 3 ++; MIPS-NEXT: xori $3, $3, 3 ++; MIPS-NEXT: sll $3, $3, 3 ++; MIPS-NEXT: ori $4, $zero, 255 ++; MIPS-NEXT: sllv $4, $4, $3 ++; MIPS-NEXT: nor $6, $zero, $4 ++; MIPS-NEXT: sllv $5, $5, $3 ++; MIPS-NEXT: $BB10_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $8, 0($2) ++; MIPS-NEXT: sltu $11, $8, $5 ++; MIPS-NEXT: move $9, $8 ++; MIPS-NEXT: movn $9, $5, $11 ++; MIPS-NEXT: and $9, $9, $4 ++; MIPS-NEXT: and $10, $8, $6 ++; MIPS-NEXT: or $10, $10, $9 ++; MIPS-NEXT: sc $10, 0($2) ++; MIPS-NEXT: beqz $10, $BB10_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: and $7, $8, $4 ++; MIPS-NEXT: srlv $7, $7, $3 ++; MIPS-NEXT: seh $7, $7 ++; MIPS-NEXT: # %bb.3: # %entry ++; MIPS-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPS-NEXT: # %bb.4: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPS-NEXT: addiu $sp, $sp, 8 ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_umax_8: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: addiu $sp, $sp, -8 ++; MIPSR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSR6-NEXT: move $1, $5 ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: addiu $2, $zero, -4 ++; MIPSR6-NEXT: and $2, $4, $2 ++; MIPSR6-NEXT: andi $3, $4, 3 ++; MIPSR6-NEXT: xori $3, $3, 3 ++; MIPSR6-NEXT: sll $3, $3, 3 ++; MIPSR6-NEXT: ori $4, $zero, 255 ++; MIPSR6-NEXT: sllv $4, $4, $3 ++; MIPSR6-NEXT: nor $6, $zero, $4 ++; MIPSR6-NEXT: sllv $5, $5, $3 ++; MIPSR6-NEXT: $BB10_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $8, 0($2) ++; MIPSR6-NEXT: sltu $11, $8, $5 ++; MIPSR6-NEXT: seleqz $9, $8, $11 ++; MIPSR6-NEXT: selnez $11, $5, $11 ++; MIPSR6-NEXT: or $9, $9, $11 ++; MIPSR6-NEXT: and $9, $9, $4 ++; MIPSR6-NEXT: and $10, $8, $6 ++; MIPSR6-NEXT: or $10, $10, $9 ++; MIPSR6-NEXT: sc $10, 0($2) ++; MIPSR6-NEXT: beqzc $10, $BB10_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: and $7, $8, $4 ++; MIPSR6-NEXT: srlv $7, $7, $3 ++; MIPSR6-NEXT: seh $7, $7 ++; MIPSR6-NEXT: # %bb.3: # %entry ++; MIPSR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSR6-NEXT: # %bb.4: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSR6-NEXT: addiu $sp, $sp, 8 ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_umax_8: ++; MM: # %bb.0: # %entry ++; MM-NEXT: addiu $sp, $sp, -8 ++; MM-NEXT: .cfi_def_cfa_offset 8 ++; MM-NEXT: move $1, $5 ++; MM-NEXT: sync ++; MM-NEXT: addiu $2, $zero, -4 ++; MM-NEXT: and $2, $4, $2 ++; MM-NEXT: andi $3, $4, 3 ++; MM-NEXT: xori $3, $3, 3 ++; MM-NEXT: sll $3, $3, 3 ++; MM-NEXT: ori $4, $zero, 255 ++; MM-NEXT: sllv $4, $4, $3 ++; MM-NEXT: nor $6, $zero, $4 ++; MM-NEXT: sllv $5, $5, $3 ++; MM-NEXT: $BB10_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $8, 0($2) ++; MM-NEXT: sltu $11, $8, $5 ++; MM-NEXT: or $9, $8, $zero ++; MM-NEXT: movn $9, $5, $11 ++; MM-NEXT: and $9, $9, $4 ++; MM-NEXT: and $10, $8, $6 ++; MM-NEXT: or $10, $10, $9 ++; MM-NEXT: sc $10, 0($2) ++; MM-NEXT: beqzc $10, $BB10_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: and $7, $8, $4 ++; MM-NEXT: srlv $7, $7, $3 ++; MM-NEXT: seh $7, $7 ++; MM-NEXT: # %bb.3: # %entry ++; MM-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MM-NEXT: # %bb.4: # %entry ++; MM-NEXT: sync ++; MM-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MM-NEXT: addiusp 8 ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_umax_8: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: addiu $sp, $sp, -8 ++; MMR6-NEXT: .cfi_def_cfa_offset 8 ++; MMR6-NEXT: move $1, $5 ++; MMR6-NEXT: sync ++; MMR6-NEXT: addiu $2, $zero, -4 ++; MMR6-NEXT: and $2, $4, $2 ++; MMR6-NEXT: andi $3, $4, 3 ++; MMR6-NEXT: xori $3, $3, 3 ++; MMR6-NEXT: sll $3, $3, 3 ++; MMR6-NEXT: ori $4, $zero, 255 ++; MMR6-NEXT: sllv $4, $4, $3 ++; MMR6-NEXT: nor $6, $zero, $4 ++; MMR6-NEXT: sllv $5, $5, $3 ++; MMR6-NEXT: $BB10_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $8, 0($2) ++; MMR6-NEXT: sltu $11, $8, $5 ++; MMR6-NEXT: seleqz $9, $8, $11 ++; MMR6-NEXT: selnez $11, $5, $11 ++; MMR6-NEXT: or $9, $9, $11 ++; MMR6-NEXT: and $9, $9, $4 ++; MMR6-NEXT: and $10, $8, $6 ++; MMR6-NEXT: or $10, $10, $9 ++; MMR6-NEXT: sc $10, 0($2) ++; MMR6-NEXT: beqc $10, $zero, $BB10_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: and $7, $8, $4 ++; MMR6-NEXT: srlv $7, $7, $3 ++; MMR6-NEXT: seh $7, $7 ++; MMR6-NEXT: # %bb.3: # %entry ++; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMR6-NEXT: # %bb.4: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMR6-NEXT: addiu $sp, $sp, 8 ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_umax_8: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: addiu $sp, $sp, -8 ++; MIPSEL-NEXT: .cfi_def_cfa_offset 8 ++; MIPSEL-NEXT: move $1, $5 ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: addiu $2, $zero, -4 ++; MIPSEL-NEXT: and $2, $4, $2 ++; MIPSEL-NEXT: andi $3, $4, 3 ++; MIPSEL-NEXT: sll $3, $3, 3 ++; MIPSEL-NEXT: ori $4, $zero, 255 ++; MIPSEL-NEXT: sllv $4, $4, $3 ++; MIPSEL-NEXT: nor $6, $zero, $4 ++; MIPSEL-NEXT: sllv $5, $5, $3 ++; MIPSEL-NEXT: $BB10_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $8, 0($2) ++; MIPSEL-NEXT: and $8, $8, $4 ++; MIPSEL-NEXT: and $5, $5, $4 ++; MIPSEL-NEXT: sltu $11, $8, $5 ++; MIPSEL-NEXT: move $9, $8 ++; MIPSEL-NEXT: movn $9, $5, $11 ++; MIPSEL-NEXT: and $9, $9, $4 ++; MIPSEL-NEXT: and $10, $8, $6 ++; MIPSEL-NEXT: or $10, $10, $9 ++; MIPSEL-NEXT: sc $10, 0($2) ++; MIPSEL-NEXT: beqz $10, $BB10_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: and $7, $8, $4 ++; MIPSEL-NEXT: srlv $7, $7, $3 ++; MIPSEL-NEXT: seh $7, $7 ++; MIPSEL-NEXT: # %bb.3: # %entry ++; MIPSEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSEL-NEXT: # %bb.4: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSEL-NEXT: addiu $sp, $sp, 8 ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_umax_8: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: addiu $sp, $sp, -8 ++; MIPSELR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSELR6-NEXT: move $1, $5 ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: addiu $2, $zero, -4 ++; MIPSELR6-NEXT: and $2, $4, $2 ++; MIPSELR6-NEXT: andi $3, $4, 3 ++; MIPSELR6-NEXT: sll $3, $3, 3 ++; MIPSELR6-NEXT: ori $4, $zero, 255 ++; MIPSELR6-NEXT: sllv $4, $4, $3 ++; MIPSELR6-NEXT: nor $6, $zero, $4 ++; MIPSELR6-NEXT: sllv $5, $5, $3 ++; MIPSELR6-NEXT: $BB10_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $8, 0($2) ++; MIPSELR6-NEXT: and $8, $8, $4 ++; MIPSELR6-NEXT: and $5, $5, $4 ++; MIPSELR6-NEXT: sltu $11, $8, $5 ++; MIPSELR6-NEXT: seleqz $9, $8, $11 ++; MIPSELR6-NEXT: selnez $11, $5, $11 ++; MIPSELR6-NEXT: or $9, $9, $11 ++; MIPSELR6-NEXT: and $9, $9, $4 ++; MIPSELR6-NEXT: and $10, $8, $6 ++; MIPSELR6-NEXT: or $10, $10, $9 ++; MIPSELR6-NEXT: sc $10, 0($2) ++; MIPSELR6-NEXT: beqzc $10, $BB10_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: and $7, $8, $4 ++; MIPSELR6-NEXT: srlv $7, $7, $3 ++; MIPSELR6-NEXT: seh $7, $7 ++; MIPSELR6-NEXT: # %bb.3: # %entry ++; MIPSELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSELR6-NEXT: # %bb.4: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSELR6-NEXT: addiu $sp, $sp, 8 ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_umax_8: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: addiu $sp, $sp, -8 ++; MMEL-NEXT: .cfi_def_cfa_offset 8 ++; MMEL-NEXT: move $1, $5 ++; MMEL-NEXT: sync ++; MMEL-NEXT: addiu $2, $zero, -4 ++; MMEL-NEXT: and $2, $4, $2 ++; MMEL-NEXT: andi $3, $4, 3 ++; MMEL-NEXT: sll $3, $3, 3 ++; MMEL-NEXT: ori $4, $zero, 255 ++; MMEL-NEXT: sllv $4, $4, $3 ++; MMEL-NEXT: nor $6, $zero, $4 ++; MMEL-NEXT: sllv $5, $5, $3 ++; MMEL-NEXT: $BB10_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $8, 0($2) ++; MMEL-NEXT: and $8, $8, $4 ++; MMEL-NEXT: and $5, $5, $4 ++; MMEL-NEXT: sltu $11, $8, $5 ++; MMEL-NEXT: or $9, $8, $zero ++; MMEL-NEXT: movn $9, $5, $11 ++; MMEL-NEXT: and $9, $9, $4 ++; MMEL-NEXT: and $10, $8, $6 ++; MMEL-NEXT: or $10, $10, $9 ++; MMEL-NEXT: sc $10, 0($2) ++; MMEL-NEXT: beqzc $10, $BB10_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: and $7, $8, $4 ++; MMEL-NEXT: srlv $7, $7, $3 ++; MMEL-NEXT: seh $7, $7 ++; MMEL-NEXT: # %bb.3: # %entry ++; MMEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMEL-NEXT: # %bb.4: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMEL-NEXT: addiusp 8 ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_umax_8: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: addiu $sp, $sp, -8 ++; MMELR6-NEXT: .cfi_def_cfa_offset 8 ++; MMELR6-NEXT: move $1, $5 ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: addiu $2, $zero, -4 ++; MMELR6-NEXT: and $2, $4, $2 ++; MMELR6-NEXT: andi $3, $4, 3 ++; MMELR6-NEXT: sll $3, $3, 3 ++; MMELR6-NEXT: ori $4, $zero, 255 ++; MMELR6-NEXT: sllv $4, $4, $3 ++; MMELR6-NEXT: nor $6, $zero, $4 ++; MMELR6-NEXT: sllv $5, $5, $3 ++; MMELR6-NEXT: $BB10_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $8, 0($2) ++; MMELR6-NEXT: and $8, $8, $4 ++; MMELR6-NEXT: and $5, $5, $4 ++; MMELR6-NEXT: sltu $11, $8, $5 ++; MMELR6-NEXT: seleqz $9, $8, $11 ++; MMELR6-NEXT: selnez $11, $5, $11 ++; MMELR6-NEXT: or $9, $9, $11 ++; MMELR6-NEXT: and $9, $9, $4 ++; MMELR6-NEXT: and $10, $8, $6 ++; MMELR6-NEXT: or $10, $10, $9 ++; MMELR6-NEXT: sc $10, 0($2) ++; MMELR6-NEXT: beqc $10, $zero, $BB10_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: and $7, $8, $4 ++; MMELR6-NEXT: srlv $7, $7, $3 ++; MMELR6-NEXT: seh $7, $7 ++; MMELR6-NEXT: # %bb.3: # %entry ++; MMELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMELR6-NEXT: # %bb.4: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMELR6-NEXT: addiu $sp, $sp, 8 ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_umax_8: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: daddiu $sp, $sp, -16 ++; MIPS64-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: daddiu $1, $zero, -4 ++; MIPS64-NEXT: and $1, $4, $1 ++; MIPS64-NEXT: andi $2, $4, 3 ++; MIPS64-NEXT: xori $2, $2, 3 ++; MIPS64-NEXT: sll $2, $2, 3 ++; MIPS64-NEXT: ori $3, $zero, 255 ++; MIPS64-NEXT: sllv $3, $3, $2 ++; MIPS64-NEXT: nor $6, $zero, $3 ++; MIPS64-NEXT: sllv $5, $5, $2 ++; MIPS64-NEXT: .LBB10_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $8, 0($1) ++; MIPS64-NEXT: sltu $11, $8, $5 ++; MIPS64-NEXT: move $9, $8 ++; MIPS64-NEXT: movn $9, $5, $11 ++; MIPS64-NEXT: and $9, $9, $3 ++; MIPS64-NEXT: and $10, $8, $6 ++; MIPS64-NEXT: or $10, $10, $9 ++; MIPS64-NEXT: sc $10, 0($1) ++; MIPS64-NEXT: beqz $10, .LBB10_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: and $7, $8, $3 ++; MIPS64-NEXT: srlv $7, $7, $2 ++; MIPS64-NEXT: seh $7, $7 ++; MIPS64-NEXT: # %bb.3: # %entry ++; MIPS64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64-NEXT: # %bb.4: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64-NEXT: daddiu $sp, $sp, 16 ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_umax_8: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64R6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: daddiu $1, $zero, -4 ++; MIPS64R6-NEXT: and $1, $4, $1 ++; MIPS64R6-NEXT: andi $2, $4, 3 ++; MIPS64R6-NEXT: xori $2, $2, 3 ++; MIPS64R6-NEXT: sll $2, $2, 3 ++; MIPS64R6-NEXT: ori $3, $zero, 255 ++; MIPS64R6-NEXT: sllv $3, $3, $2 ++; MIPS64R6-NEXT: nor $6, $zero, $3 ++; MIPS64R6-NEXT: sllv $5, $5, $2 ++; MIPS64R6-NEXT: .LBB10_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $8, 0($1) ++; MIPS64R6-NEXT: sltu $11, $8, $5 ++; MIPS64R6-NEXT: seleqz $9, $8, $11 ++; MIPS64R6-NEXT: selnez $11, $5, $11 ++; MIPS64R6-NEXT: or $9, $9, $11 ++; MIPS64R6-NEXT: and $9, $9, $3 ++; MIPS64R6-NEXT: and $10, $8, $6 ++; MIPS64R6-NEXT: or $10, $10, $9 ++; MIPS64R6-NEXT: sc $10, 0($1) ++; MIPS64R6-NEXT: beqzc $10, .LBB10_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: and $7, $8, $3 ++; MIPS64R6-NEXT: srlv $7, $7, $2 ++; MIPS64R6-NEXT: seh $7, $7 ++; MIPS64R6-NEXT: # %bb.3: # %entry ++; MIPS64R6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64R6-NEXT: # %bb.4: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64R6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_umax_8: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: daddiu $sp, $sp, -16 ++; MIPS64EL-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: daddiu $1, $zero, -4 ++; MIPS64EL-NEXT: and $1, $4, $1 ++; MIPS64EL-NEXT: andi $2, $4, 3 ++; MIPS64EL-NEXT: sll $2, $2, 3 ++; MIPS64EL-NEXT: ori $3, $zero, 255 ++; MIPS64EL-NEXT: sllv $3, $3, $2 ++; MIPS64EL-NEXT: nor $6, $zero, $3 ++; MIPS64EL-NEXT: sllv $5, $5, $2 ++; MIPS64EL-NEXT: .LBB10_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $8, 0($1) ++; MIPS64EL-NEXT: and $8, $8, $3 ++; MIPS64EL-NEXT: and $5, $5, $3 ++; MIPS64EL-NEXT: sltu $11, $8, $5 ++; MIPS64EL-NEXT: move $9, $8 ++; MIPS64EL-NEXT: movn $9, $5, $11 ++; MIPS64EL-NEXT: and $9, $9, $3 ++; MIPS64EL-NEXT: and $10, $8, $6 ++; MIPS64EL-NEXT: or $10, $10, $9 ++; MIPS64EL-NEXT: sc $10, 0($1) ++; MIPS64EL-NEXT: beqz $10, .LBB10_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: and $7, $8, $3 ++; MIPS64EL-NEXT: srlv $7, $7, $2 ++; MIPS64EL-NEXT: seh $7, $7 ++; MIPS64EL-NEXT: # %bb.3: # %entry ++; MIPS64EL-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64EL-NEXT: # %bb.4: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64EL-NEXT: daddiu $sp, $sp, 16 ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_umax_8: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64ELR6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: daddiu $1, $zero, -4 ++; MIPS64ELR6-NEXT: and $1, $4, $1 ++; MIPS64ELR6-NEXT: andi $2, $4, 3 ++; MIPS64ELR6-NEXT: sll $2, $2, 3 ++; MIPS64ELR6-NEXT: ori $3, $zero, 255 ++; MIPS64ELR6-NEXT: sllv $3, $3, $2 ++; MIPS64ELR6-NEXT: nor $6, $zero, $3 ++; MIPS64ELR6-NEXT: sllv $5, $5, $2 ++; MIPS64ELR6-NEXT: .LBB10_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $8, 0($1) ++; MIPS64ELR6-NEXT: and $8, $8, $3 ++; MIPS64ELR6-NEXT: and $5, $5, $3 ++; MIPS64ELR6-NEXT: sltu $11, $8, $5 ++; MIPS64ELR6-NEXT: seleqz $9, $8, $11 ++; MIPS64ELR6-NEXT: selnez $11, $5, $11 ++; MIPS64ELR6-NEXT: or $9, $9, $11 ++; MIPS64ELR6-NEXT: and $9, $9, $3 ++; MIPS64ELR6-NEXT: and $10, $8, $6 ++; MIPS64ELR6-NEXT: or $10, $10, $9 ++; MIPS64ELR6-NEXT: sc $10, 0($1) ++; MIPS64ELR6-NEXT: beqzc $10, .LBB10_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: and $7, $8, $3 ++; MIPS64ELR6-NEXT: srlv $7, $7, $2 ++; MIPS64ELR6-NEXT: seh $7, $7 ++; MIPS64ELR6-NEXT: # %bb.3: # %entry ++; MIPS64ELR6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64ELR6-NEXT: # %bb.4: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw umax i8* %ptr, i8 %val seq_cst ++ ret i8 %0 ++} ++ ++define i8 @test_umin_8(i8* nocapture %ptr, i8 signext %val) { ++; MIPS-LABEL: test_umin_8: ++; MIPS: # %bb.0: # %entry ++; MIPS-NEXT: addiu $sp, $sp, -8 ++; MIPS-NEXT: .cfi_def_cfa_offset 8 ++; MIPS-NEXT: move $1, $5 ++; MIPS-NEXT: sync ++; MIPS-NEXT: addiu $2, $zero, -4 ++; MIPS-NEXT: and $2, $4, $2 ++; MIPS-NEXT: andi $3, $4, 3 ++; MIPS-NEXT: xori $3, $3, 3 ++; MIPS-NEXT: sll $3, $3, 3 ++; MIPS-NEXT: ori $4, $zero, 255 ++; MIPS-NEXT: sllv $4, $4, $3 ++; MIPS-NEXT: nor $6, $zero, $4 ++; MIPS-NEXT: sllv $5, $5, $3 ++; MIPS-NEXT: $BB11_1: # %entry ++; MIPS-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS-NEXT: ll $8, 0($2) ++; MIPS-NEXT: sltu $11, $8, $5 ++; MIPS-NEXT: move $9, $8 ++; MIPS-NEXT: movz $9, $5, $11 ++; MIPS-NEXT: and $9, $9, $4 ++; MIPS-NEXT: and $10, $8, $6 ++; MIPS-NEXT: or $10, $10, $9 ++; MIPS-NEXT: sc $10, 0($2) ++; MIPS-NEXT: beqz $10, $BB11_1 ++; MIPS-NEXT: nop ++; MIPS-NEXT: # %bb.2: # %entry ++; MIPS-NEXT: and $7, $8, $4 ++; MIPS-NEXT: srlv $7, $7, $3 ++; MIPS-NEXT: seh $7, $7 ++; MIPS-NEXT: # %bb.3: # %entry ++; MIPS-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPS-NEXT: # %bb.4: # %entry ++; MIPS-NEXT: sync ++; MIPS-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPS-NEXT: addiu $sp, $sp, 8 ++; MIPS-NEXT: jr $ra ++; MIPS-NEXT: nop ++; ++; MIPSR6-LABEL: test_umin_8: ++; MIPSR6: # %bb.0: # %entry ++; MIPSR6-NEXT: addiu $sp, $sp, -8 ++; MIPSR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSR6-NEXT: move $1, $5 ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: addiu $2, $zero, -4 ++; MIPSR6-NEXT: and $2, $4, $2 ++; MIPSR6-NEXT: andi $3, $4, 3 ++; MIPSR6-NEXT: xori $3, $3, 3 ++; MIPSR6-NEXT: sll $3, $3, 3 ++; MIPSR6-NEXT: ori $4, $zero, 255 ++; MIPSR6-NEXT: sllv $4, $4, $3 ++; MIPSR6-NEXT: nor $6, $zero, $4 ++; MIPSR6-NEXT: sllv $5, $5, $3 ++; MIPSR6-NEXT: $BB11_1: # %entry ++; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSR6-NEXT: ll $8, 0($2) ++; MIPSR6-NEXT: sltu $11, $8, $5 ++; MIPSR6-NEXT: selnez $9, $8, $11 ++; MIPSR6-NEXT: seleqz $11, $5, $11 ++; MIPSR6-NEXT: or $9, $9, $11 ++; MIPSR6-NEXT: and $9, $9, $4 ++; MIPSR6-NEXT: and $10, $8, $6 ++; MIPSR6-NEXT: or $10, $10, $9 ++; MIPSR6-NEXT: sc $10, 0($2) ++; MIPSR6-NEXT: beqzc $10, $BB11_1 ++; MIPSR6-NEXT: # %bb.2: # %entry ++; MIPSR6-NEXT: and $7, $8, $4 ++; MIPSR6-NEXT: srlv $7, $7, $3 ++; MIPSR6-NEXT: seh $7, $7 ++; MIPSR6-NEXT: # %bb.3: # %entry ++; MIPSR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSR6-NEXT: # %bb.4: # %entry ++; MIPSR6-NEXT: sync ++; MIPSR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSR6-NEXT: addiu $sp, $sp, 8 ++; MIPSR6-NEXT: jrc $ra ++; ++; MM-LABEL: test_umin_8: ++; MM: # %bb.0: # %entry ++; MM-NEXT: addiu $sp, $sp, -8 ++; MM-NEXT: .cfi_def_cfa_offset 8 ++; MM-NEXT: move $1, $5 ++; MM-NEXT: sync ++; MM-NEXT: addiu $2, $zero, -4 ++; MM-NEXT: and $2, $4, $2 ++; MM-NEXT: andi $3, $4, 3 ++; MM-NEXT: xori $3, $3, 3 ++; MM-NEXT: sll $3, $3, 3 ++; MM-NEXT: ori $4, $zero, 255 ++; MM-NEXT: sllv $4, $4, $3 ++; MM-NEXT: nor $6, $zero, $4 ++; MM-NEXT: sllv $5, $5, $3 ++; MM-NEXT: $BB11_1: # %entry ++; MM-NEXT: # =>This Inner Loop Header: Depth=1 ++; MM-NEXT: ll $8, 0($2) ++; MM-NEXT: sltu $11, $8, $5 ++; MM-NEXT: or $9, $8, $zero ++; MM-NEXT: movz $9, $5, $11 ++; MM-NEXT: and $9, $9, $4 ++; MM-NEXT: and $10, $8, $6 ++; MM-NEXT: or $10, $10, $9 ++; MM-NEXT: sc $10, 0($2) ++; MM-NEXT: beqzc $10, $BB11_1 ++; MM-NEXT: # %bb.2: # %entry ++; MM-NEXT: and $7, $8, $4 ++; MM-NEXT: srlv $7, $7, $3 ++; MM-NEXT: seh $7, $7 ++; MM-NEXT: # %bb.3: # %entry ++; MM-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MM-NEXT: # %bb.4: # %entry ++; MM-NEXT: sync ++; MM-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MM-NEXT: addiusp 8 ++; MM-NEXT: jrc $ra ++; ++; MMR6-LABEL: test_umin_8: ++; MMR6: # %bb.0: # %entry ++; MMR6-NEXT: addiu $sp, $sp, -8 ++; MMR6-NEXT: .cfi_def_cfa_offset 8 ++; MMR6-NEXT: move $1, $5 ++; MMR6-NEXT: sync ++; MMR6-NEXT: addiu $2, $zero, -4 ++; MMR6-NEXT: and $2, $4, $2 ++; MMR6-NEXT: andi $3, $4, 3 ++; MMR6-NEXT: xori $3, $3, 3 ++; MMR6-NEXT: sll $3, $3, 3 ++; MMR6-NEXT: ori $4, $zero, 255 ++; MMR6-NEXT: sllv $4, $4, $3 ++; MMR6-NEXT: nor $6, $zero, $4 ++; MMR6-NEXT: sllv $5, $5, $3 ++; MMR6-NEXT: $BB11_1: # %entry ++; MMR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMR6-NEXT: ll $8, 0($2) ++; MMR6-NEXT: sltu $11, $8, $5 ++; MMR6-NEXT: selnez $9, $8, $11 ++; MMR6-NEXT: seleqz $11, $5, $11 ++; MMR6-NEXT: or $9, $9, $11 ++; MMR6-NEXT: and $9, $9, $4 ++; MMR6-NEXT: and $10, $8, $6 ++; MMR6-NEXT: or $10, $10, $9 ++; MMR6-NEXT: sc $10, 0($2) ++; MMR6-NEXT: beqc $10, $zero, $BB11_1 ++; MMR6-NEXT: # %bb.2: # %entry ++; MMR6-NEXT: and $7, $8, $4 ++; MMR6-NEXT: srlv $7, $7, $3 ++; MMR6-NEXT: seh $7, $7 ++; MMR6-NEXT: # %bb.3: # %entry ++; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMR6-NEXT: # %bb.4: # %entry ++; MMR6-NEXT: sync ++; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMR6-NEXT: addiu $sp, $sp, 8 ++; MMR6-NEXT: jrc $ra ++; ++; MIPSEL-LABEL: test_umin_8: ++; MIPSEL: # %bb.0: # %entry ++; MIPSEL-NEXT: addiu $sp, $sp, -8 ++; MIPSEL-NEXT: .cfi_def_cfa_offset 8 ++; MIPSEL-NEXT: move $1, $5 ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: addiu $2, $zero, -4 ++; MIPSEL-NEXT: and $2, $4, $2 ++; MIPSEL-NEXT: andi $3, $4, 3 ++; MIPSEL-NEXT: sll $3, $3, 3 ++; MIPSEL-NEXT: ori $4, $zero, 255 ++; MIPSEL-NEXT: sllv $4, $4, $3 ++; MIPSEL-NEXT: nor $6, $zero, $4 ++; MIPSEL-NEXT: sllv $5, $5, $3 ++; MIPSEL-NEXT: $BB11_1: # %entry ++; MIPSEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSEL-NEXT: ll $8, 0($2) ++; MIPSEL-NEXT: and $8, $8, $4 ++; MIPSEL-NEXT: and $5, $5, $4 ++; MIPSEL-NEXT: sltu $11, $8, $5 ++; MIPSEL-NEXT: move $9, $8 ++; MIPSEL-NEXT: movz $9, $5, $11 ++; MIPSEL-NEXT: and $9, $9, $4 ++; MIPSEL-NEXT: and $10, $8, $6 ++; MIPSEL-NEXT: or $10, $10, $9 ++; MIPSEL-NEXT: sc $10, 0($2) ++; MIPSEL-NEXT: beqz $10, $BB11_1 ++; MIPSEL-NEXT: nop ++; MIPSEL-NEXT: # %bb.2: # %entry ++; MIPSEL-NEXT: and $7, $8, $4 ++; MIPSEL-NEXT: srlv $7, $7, $3 ++; MIPSEL-NEXT: seh $7, $7 ++; MIPSEL-NEXT: # %bb.3: # %entry ++; MIPSEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSEL-NEXT: # %bb.4: # %entry ++; MIPSEL-NEXT: sync ++; MIPSEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSEL-NEXT: addiu $sp, $sp, 8 ++; MIPSEL-NEXT: jr $ra ++; MIPSEL-NEXT: nop ++; ++; MIPSELR6-LABEL: test_umin_8: ++; MIPSELR6: # %bb.0: # %entry ++; MIPSELR6-NEXT: addiu $sp, $sp, -8 ++; MIPSELR6-NEXT: .cfi_def_cfa_offset 8 ++; MIPSELR6-NEXT: move $1, $5 ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: addiu $2, $zero, -4 ++; MIPSELR6-NEXT: and $2, $4, $2 ++; MIPSELR6-NEXT: andi $3, $4, 3 ++; MIPSELR6-NEXT: sll $3, $3, 3 ++; MIPSELR6-NEXT: ori $4, $zero, 255 ++; MIPSELR6-NEXT: sllv $4, $4, $3 ++; MIPSELR6-NEXT: nor $6, $zero, $4 ++; MIPSELR6-NEXT: sllv $5, $5, $3 ++; MIPSELR6-NEXT: $BB11_1: # %entry ++; MIPSELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPSELR6-NEXT: ll $8, 0($2) ++; MIPSELR6-NEXT: and $8, $8, $4 ++; MIPSELR6-NEXT: and $5, $5, $4 ++; MIPSELR6-NEXT: sltu $11, $8, $5 ++; MIPSELR6-NEXT: selnez $9, $8, $11 ++; MIPSELR6-NEXT: seleqz $11, $5, $11 ++; MIPSELR6-NEXT: or $9, $9, $11 ++; MIPSELR6-NEXT: and $9, $9, $4 ++; MIPSELR6-NEXT: and $10, $8, $6 ++; MIPSELR6-NEXT: or $10, $10, $9 ++; MIPSELR6-NEXT: sc $10, 0($2) ++; MIPSELR6-NEXT: beqzc $10, $BB11_1 ++; MIPSELR6-NEXT: # %bb.2: # %entry ++; MIPSELR6-NEXT: and $7, $8, $4 ++; MIPSELR6-NEXT: srlv $7, $7, $3 ++; MIPSELR6-NEXT: seh $7, $7 ++; MIPSELR6-NEXT: # %bb.3: # %entry ++; MIPSELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MIPSELR6-NEXT: # %bb.4: # %entry ++; MIPSELR6-NEXT: sync ++; MIPSELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MIPSELR6-NEXT: addiu $sp, $sp, 8 ++; MIPSELR6-NEXT: jrc $ra ++; ++; MMEL-LABEL: test_umin_8: ++; MMEL: # %bb.0: # %entry ++; MMEL-NEXT: addiu $sp, $sp, -8 ++; MMEL-NEXT: .cfi_def_cfa_offset 8 ++; MMEL-NEXT: move $1, $5 ++; MMEL-NEXT: sync ++; MMEL-NEXT: addiu $2, $zero, -4 ++; MMEL-NEXT: and $2, $4, $2 ++; MMEL-NEXT: andi $3, $4, 3 ++; MMEL-NEXT: sll $3, $3, 3 ++; MMEL-NEXT: ori $4, $zero, 255 ++; MMEL-NEXT: sllv $4, $4, $3 ++; MMEL-NEXT: nor $6, $zero, $4 ++; MMEL-NEXT: sllv $5, $5, $3 ++; MMEL-NEXT: $BB11_1: # %entry ++; MMEL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMEL-NEXT: ll $8, 0($2) ++; MMEL-NEXT: and $8, $8, $4 ++; MMEL-NEXT: and $5, $5, $4 ++; MMEL-NEXT: sltu $11, $8, $5 ++; MMEL-NEXT: or $9, $8, $zero ++; MMEL-NEXT: movz $9, $5, $11 ++; MMEL-NEXT: and $9, $9, $4 ++; MMEL-NEXT: and $10, $8, $6 ++; MMEL-NEXT: or $10, $10, $9 ++; MMEL-NEXT: sc $10, 0($2) ++; MMEL-NEXT: beqzc $10, $BB11_1 ++; MMEL-NEXT: # %bb.2: # %entry ++; MMEL-NEXT: and $7, $8, $4 ++; MMEL-NEXT: srlv $7, $7, $3 ++; MMEL-NEXT: seh $7, $7 ++; MMEL-NEXT: # %bb.3: # %entry ++; MMEL-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMEL-NEXT: # %bb.4: # %entry ++; MMEL-NEXT: sync ++; MMEL-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMEL-NEXT: addiusp 8 ++; MMEL-NEXT: jrc $ra ++; ++; MMELR6-LABEL: test_umin_8: ++; MMELR6: # %bb.0: # %entry ++; MMELR6-NEXT: addiu $sp, $sp, -8 ++; MMELR6-NEXT: .cfi_def_cfa_offset 8 ++; MMELR6-NEXT: move $1, $5 ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: addiu $2, $zero, -4 ++; MMELR6-NEXT: and $2, $4, $2 ++; MMELR6-NEXT: andi $3, $4, 3 ++; MMELR6-NEXT: sll $3, $3, 3 ++; MMELR6-NEXT: ori $4, $zero, 255 ++; MMELR6-NEXT: sllv $4, $4, $3 ++; MMELR6-NEXT: nor $6, $zero, $4 ++; MMELR6-NEXT: sllv $5, $5, $3 ++; MMELR6-NEXT: $BB11_1: # %entry ++; MMELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MMELR6-NEXT: ll $8, 0($2) ++; MMELR6-NEXT: and $8, $8, $4 ++; MMELR6-NEXT: and $5, $5, $4 ++; MMELR6-NEXT: sltu $11, $8, $5 ++; MMELR6-NEXT: selnez $9, $8, $11 ++; MMELR6-NEXT: seleqz $11, $5, $11 ++; MMELR6-NEXT: or $9, $9, $11 ++; MMELR6-NEXT: and $9, $9, $4 ++; MMELR6-NEXT: and $10, $8, $6 ++; MMELR6-NEXT: or $10, $10, $9 ++; MMELR6-NEXT: sc $10, 0($2) ++; MMELR6-NEXT: beqc $10, $zero, $BB11_1 ++; MMELR6-NEXT: # %bb.2: # %entry ++; MMELR6-NEXT: and $7, $8, $4 ++; MMELR6-NEXT: srlv $7, $7, $3 ++; MMELR6-NEXT: seh $7, $7 ++; MMELR6-NEXT: # %bb.3: # %entry ++; MMELR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill ++; MMELR6-NEXT: # %bb.4: # %entry ++; MMELR6-NEXT: sync ++; MMELR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload ++; MMELR6-NEXT: addiu $sp, $sp, 8 ++; MMELR6-NEXT: jrc $ra ++; ++; MIPS64-LABEL: test_umin_8: ++; MIPS64: # %bb.0: # %entry ++; MIPS64-NEXT: daddiu $sp, $sp, -16 ++; MIPS64-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: daddiu $1, $zero, -4 ++; MIPS64-NEXT: and $1, $4, $1 ++; MIPS64-NEXT: andi $2, $4, 3 ++; MIPS64-NEXT: xori $2, $2, 3 ++; MIPS64-NEXT: sll $2, $2, 3 ++; MIPS64-NEXT: ori $3, $zero, 255 ++; MIPS64-NEXT: sllv $3, $3, $2 ++; MIPS64-NEXT: nor $6, $zero, $3 ++; MIPS64-NEXT: sllv $5, $5, $2 ++; MIPS64-NEXT: .LBB11_1: # %entry ++; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64-NEXT: ll $8, 0($1) ++; MIPS64-NEXT: sltu $11, $8, $5 ++; MIPS64-NEXT: move $9, $8 ++; MIPS64-NEXT: movz $9, $5, $11 ++; MIPS64-NEXT: and $9, $9, $3 ++; MIPS64-NEXT: and $10, $8, $6 ++; MIPS64-NEXT: or $10, $10, $9 ++; MIPS64-NEXT: sc $10, 0($1) ++; MIPS64-NEXT: beqz $10, .LBB11_1 ++; MIPS64-NEXT: nop ++; MIPS64-NEXT: # %bb.2: # %entry ++; MIPS64-NEXT: and $7, $8, $3 ++; MIPS64-NEXT: srlv $7, $7, $2 ++; MIPS64-NEXT: seh $7, $7 ++; MIPS64-NEXT: # %bb.3: # %entry ++; MIPS64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64-NEXT: # %bb.4: # %entry ++; MIPS64-NEXT: sync ++; MIPS64-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64-NEXT: daddiu $sp, $sp, 16 ++; MIPS64-NEXT: jr $ra ++; MIPS64-NEXT: nop ++; ++; MIPS64R6-LABEL: test_umin_8: ++; MIPS64R6: # %bb.0: # %entry ++; MIPS64R6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64R6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64R6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: daddiu $1, $zero, -4 ++; MIPS64R6-NEXT: and $1, $4, $1 ++; MIPS64R6-NEXT: andi $2, $4, 3 ++; MIPS64R6-NEXT: xori $2, $2, 3 ++; MIPS64R6-NEXT: sll $2, $2, 3 ++; MIPS64R6-NEXT: ori $3, $zero, 255 ++; MIPS64R6-NEXT: sllv $3, $3, $2 ++; MIPS64R6-NEXT: nor $6, $zero, $3 ++; MIPS64R6-NEXT: sllv $5, $5, $2 ++; MIPS64R6-NEXT: .LBB11_1: # %entry ++; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64R6-NEXT: ll $8, 0($1) ++; MIPS64R6-NEXT: sltu $11, $8, $5 ++; MIPS64R6-NEXT: selnez $9, $8, $11 ++; MIPS64R6-NEXT: seleqz $11, $5, $11 ++; MIPS64R6-NEXT: or $9, $9, $11 ++; MIPS64R6-NEXT: and $9, $9, $3 ++; MIPS64R6-NEXT: and $10, $8, $6 ++; MIPS64R6-NEXT: or $10, $10, $9 ++; MIPS64R6-NEXT: sc $10, 0($1) ++; MIPS64R6-NEXT: beqzc $10, .LBB11_1 ++; MIPS64R6-NEXT: # %bb.2: # %entry ++; MIPS64R6-NEXT: and $7, $8, $3 ++; MIPS64R6-NEXT: srlv $7, $7, $2 ++; MIPS64R6-NEXT: seh $7, $7 ++; MIPS64R6-NEXT: # %bb.3: # %entry ++; MIPS64R6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64R6-NEXT: # %bb.4: # %entry ++; MIPS64R6-NEXT: sync ++; MIPS64R6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64R6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64R6-NEXT: jrc $ra ++; ++; MIPS64EL-LABEL: test_umin_8: ++; MIPS64EL: # %bb.0: # %entry ++; MIPS64EL-NEXT: daddiu $sp, $sp, -16 ++; MIPS64EL-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64EL-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: daddiu $1, $zero, -4 ++; MIPS64EL-NEXT: and $1, $4, $1 ++; MIPS64EL-NEXT: andi $2, $4, 3 ++; MIPS64EL-NEXT: sll $2, $2, 3 ++; MIPS64EL-NEXT: ori $3, $zero, 255 ++; MIPS64EL-NEXT: sllv $3, $3, $2 ++; MIPS64EL-NEXT: nor $6, $zero, $3 ++; MIPS64EL-NEXT: sllv $5, $5, $2 ++; MIPS64EL-NEXT: .LBB11_1: # %entry ++; MIPS64EL-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64EL-NEXT: ll $8, 0($1) ++; MIPS64EL-NEXT: and $8, $8, $3 ++; MIPS64EL-NEXT: and $5, $5, $3 ++; MIPS64EL-NEXT: sltu $11, $8, $5 ++; MIPS64EL-NEXT: move $9, $8 ++; MIPS64EL-NEXT: movz $9, $5, $11 ++; MIPS64EL-NEXT: and $9, $9, $3 ++; MIPS64EL-NEXT: and $10, $8, $6 ++; MIPS64EL-NEXT: or $10, $10, $9 ++; MIPS64EL-NEXT: sc $10, 0($1) ++; MIPS64EL-NEXT: beqz $10, .LBB11_1 ++; MIPS64EL-NEXT: nop ++; MIPS64EL-NEXT: # %bb.2: # %entry ++; MIPS64EL-NEXT: and $7, $8, $3 ++; MIPS64EL-NEXT: srlv $7, $7, $2 ++; MIPS64EL-NEXT: seh $7, $7 ++; MIPS64EL-NEXT: # %bb.3: # %entry ++; MIPS64EL-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64EL-NEXT: # %bb.4: # %entry ++; MIPS64EL-NEXT: sync ++; MIPS64EL-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64EL-NEXT: daddiu $sp, $sp, 16 ++; MIPS64EL-NEXT: jr $ra ++; MIPS64EL-NEXT: nop ++; ++; MIPS64ELR6-LABEL: test_umin_8: ++; MIPS64ELR6: # %bb.0: # %entry ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, -16 ++; MIPS64ELR6-NEXT: .cfi_def_cfa_offset 16 ++; MIPS64ELR6-NEXT: # kill: def $a1 killed $a1 killed $a1_64 ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: daddiu $1, $zero, -4 ++; MIPS64ELR6-NEXT: and $1, $4, $1 ++; MIPS64ELR6-NEXT: andi $2, $4, 3 ++; MIPS64ELR6-NEXT: sll $2, $2, 3 ++; MIPS64ELR6-NEXT: ori $3, $zero, 255 ++; MIPS64ELR6-NEXT: sllv $3, $3, $2 ++; MIPS64ELR6-NEXT: nor $6, $zero, $3 ++; MIPS64ELR6-NEXT: sllv $5, $5, $2 ++; MIPS64ELR6-NEXT: .LBB11_1: # %entry ++; MIPS64ELR6-NEXT: # =>This Inner Loop Header: Depth=1 ++; MIPS64ELR6-NEXT: ll $8, 0($1) ++; MIPS64ELR6-NEXT: and $8, $8, $3 ++; MIPS64ELR6-NEXT: and $5, $5, $3 ++; MIPS64ELR6-NEXT: sltu $11, $8, $5 ++; MIPS64ELR6-NEXT: selnez $9, $8, $11 ++; MIPS64ELR6-NEXT: seleqz $11, $5, $11 ++; MIPS64ELR6-NEXT: or $9, $9, $11 ++; MIPS64ELR6-NEXT: and $9, $9, $3 ++; MIPS64ELR6-NEXT: and $10, $8, $6 ++; MIPS64ELR6-NEXT: or $10, $10, $9 ++; MIPS64ELR6-NEXT: sc $10, 0($1) ++; MIPS64ELR6-NEXT: beqzc $10, .LBB11_1 ++; MIPS64ELR6-NEXT: # %bb.2: # %entry ++; MIPS64ELR6-NEXT: and $7, $8, $3 ++; MIPS64ELR6-NEXT: srlv $7, $7, $2 ++; MIPS64ELR6-NEXT: seh $7, $7 ++; MIPS64ELR6-NEXT: # %bb.3: # %entry ++; MIPS64ELR6-NEXT: sw $7, 12($sp) # 4-byte Folded Spill ++; MIPS64ELR6-NEXT: # %bb.4: # %entry ++; MIPS64ELR6-NEXT: sync ++; MIPS64ELR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload ++; MIPS64ELR6-NEXT: daddiu $sp, $sp, 16 ++; MIPS64ELR6-NEXT: jrc $ra ++entry: ++ %0 = atomicrmw umin i8* %ptr, i8 %val seq_cst ++ ret i8 %0 ++} +Index: llvm-toolchain-9-9.0.1~+rc3/llvm/test/CodeGen/Mips/atomic.ll +=================================================================== +--- llvm-toolchain-9-9.0.1~+rc3.orig/llvm/test/CodeGen/Mips/atomic.ll ++++ llvm-toolchain-9-9.0.1~+rc3/llvm/test/CodeGen/Mips/atomic.ll +@@ -1790,7 +1790,7 @@ define i32 @AtomicSwap32(i32 signext %ne + ; MM32-NEXT: $BB6_1: # %entry + ; MM32-NEXT: # =>This Inner Loop Header: Depth=1 + ; MM32-NEXT: ll $2, 0($1) +-; MM32-NEXT: move $3, $4 ++; MM32-NEXT: or $3, $4, $zero + ; MM32-NEXT: sc $3, 0($1) + ; MM32-NEXT: beqzc $3, $BB6_1 + ; MM32-NEXT: # %bb.2: # %entry diff --git a/debian/patches/force-gcc-header-obj.diff b/debian/patches/force-gcc-header-obj.diff deleted file mode 100644 index e47d28c3..00000000 --- a/debian/patches/force-gcc-header-obj.diff +++ /dev/null @@ -1,16 +0,0 @@ -Index: llvm-toolchain-5.0-5.0.2~+rc1/clang/lib/Driver/ToolChains/Linux.cpp -=================================================================== ---- llvm-toolchain-5.0-5.0.2~+rc1.orig/clang/lib/Driver/ToolChains/Linux.cpp -+++ llvm-toolchain-5.0-5.0.2~+rc1/clang/lib/Driver/ToolChains/Linux.cpp -@@ -571,6 +571,11 @@ void Linux::AddClangSystemIncludeArgs(co - return; - } - -+ // Force the inclusion of the gcc headers (objc/objc.h) -+ addExternCSystemIncludeIfExists( -+ DriverArgs, CC1Args, GCCInstallation.getInstallPath() + "/include"); -+// std::cout << GCCInstallation.getInstallPath().str() << "/include" << std::endl; -+ - // Lacking those, try to detect the correct set of system includes for the - // target triple. - diff --git a/debian/patches/hurd-pathmax.diff b/debian/patches/hurd-pathmax.diff deleted file mode 100644 index 089ba8d9..00000000 --- a/debian/patches/hurd-pathmax.diff +++ /dev/null @@ -1,48 +0,0 @@ -Index: llvm-toolchain-snapshot_9~svn352610/lldb/include/lldb/lldb-defines.h -=================================================================== ---- llvm-toolchain-snapshot_9~svn352610.orig/lldb/include/lldb/lldb-defines.h -+++ llvm-toolchain-snapshot_9~svn352610/lldb/include/lldb/lldb-defines.h -@@ -27,6 +27,11 @@ - #define INT32_MAX 2147483647 - #endif - -+// For GNU Hurd -+#if defined(__GNU__) && !defined(PATH_MAX) -+# define PATH_MAX 4096 -+#endif -+ - #if !defined(UINT32_MAX) - #define UINT32_MAX 4294967295U - #endif -Index: llvm-toolchain-snapshot_9~svn352610/llvm/tools/dsymutil/DwarfLinker.cpp -=================================================================== ---- llvm-toolchain-snapshot_9~svn352610.orig/llvm/tools/dsymutil/DwarfLinker.cpp -+++ llvm-toolchain-snapshot_9~svn352610/llvm/tools/dsymutil/DwarfLinker.cpp -@@ -100,6 +100,11 @@ - #include - #include - -+// For GNU Hurd -+#if defined(__GNU__) && !defined(PATH_MAX) -+# define PATH_MAX 4096 -+#endif -+ - namespace llvm { - namespace dsymutil { - -Index: llvm-toolchain-snapshot_9~svn352610/polly/lib/External/ppcg/cuda_common.c -=================================================================== ---- llvm-toolchain-snapshot_9~svn352610.orig/polly/lib/External/ppcg/cuda_common.c -+++ llvm-toolchain-snapshot_9~svn352610/polly/lib/External/ppcg/cuda_common.c -@@ -15,6 +15,11 @@ - #include "cuda_common.h" - #include "ppcg.h" - -+// For GNU Hurd -+#if defined(__GNU__) && !defined(PATH_MAX) -+# define PATH_MAX 4096 -+#endif -+ - /* Open the host .cu file and the kernel .hu and .cu files for writing. - * Add the necessary includes. - */ diff --git a/debian/patches/impl-path-hurd.diff b/debian/patches/impl-path-hurd.diff deleted file mode 100644 index 6717f4e4..00000000 --- a/debian/patches/impl-path-hurd.diff +++ /dev/null @@ -1,13 +0,0 @@ -Index: llvm-toolchain-snapshot_9~svn351647/lib/Support/Unix/Path.inc -=================================================================== ---- llvm-toolchain-snapshot_9~svn351647.orig/lib/Support/Unix/Path.inc -+++ llvm-toolchain-snapshot_9~svn351647/lib/Support/Unix/Path.inc -@@ -176,7 +176,7 @@ std::string getMainExecutable(const char - - if (getprogpath(exe_path, argv0) != NULL) - return exe_path; --#elif defined(__linux__) || defined(__CYGWIN__) -+#elif defined(__linux__) || defined(__CYGWIN__) || defined(__GNU__) - char exe_path[MAXPATHLEN]; - StringRef aPath("/proc/self/exe"); - if (sys::fs::exists(aPath)) { diff --git a/debian/patches/libcxxabi-arm-ehabi-fix.patch b/debian/patches/libcxxabi-arm-ehabi-fix.patch deleted file mode 100644 index d486eab0..00000000 --- a/debian/patches/libcxxabi-arm-ehabi-fix.patch +++ /dev/null @@ -1,118 +0,0 @@ -Fix arm EHABI code to work. armhf had exception test failing without EHABI support. - -No known upstream bug about this. Actual code change is more like workaround than -something that upstream would accept. Proper fix would be adding _Unwind_Control_Block -to clang unwind.h. _Unwind_Control_Block should also extend _Unwind_Exception to make -sure their ABI stays in sync. - -No known upstream bug about this. - -Index: llvm-toolchain-snapshot_9~svn351647/libcxxabi/src/cxa_exception.cpp -=================================================================== ---- llvm-toolchain-snapshot_9~svn351647.orig/libcxxabi/src/cxa_exception.cpp -+++ llvm-toolchain-snapshot_9~svn351647/libcxxabi/src/cxa_exception.cpp -@@ -277,15 +277,16 @@ __cxa_throw(void *thrown_object, std::ty - - #ifdef __USING_SJLJ_EXCEPTIONS__ - _Unwind_SjLj_RaiseException(&exception_header->unwindHeader); --#else -+#elif !LIBCXXABI_ARM_EHABI - _Unwind_RaiseException(&exception_header->unwindHeader); -+#else -+ _Unwind_RaiseException(exception_header->unwindHeader); - #endif - // This only happens when there is no handler, or some unexpected unwinding - // error happens. - failed_throw(exception_header); - } - -- - // 2.5.3 Exception Handlers - /* - The adjusted pointer is computed by the personality routine during phase 1 -@@ -548,7 +549,11 @@ void __cxa_end_catch() { - // to touch a foreign exception in any way, that is undefined - // behavior. They likely can't since the only way to catch - // a foreign exception is with catch (...)! -+#if !LIBCXXABI_ARM_EHABI - _Unwind_DeleteException(&globals->caughtExceptions->unwindHeader); -+#else -+ _Unwind_DeleteException(globals->caughtExceptions->unwindHeader); -+#endif - globals->caughtExceptions = 0; - } - } -@@ -605,8 +610,10 @@ void __cxa_rethrow() { - } - #ifdef __USING_SJLJ_EXCEPTIONS__ - _Unwind_SjLj_RaiseException(&exception_header->unwindHeader); --#else -+#elif !LIBCXXABI_ARM_EHABI - _Unwind_RaiseException(&exception_header->unwindHeader); -+#else -+ _Unwind_RaiseException(exception_header->unwindHeader); - #endif - - // If we get here, some kind of unwinding error has occurred. -@@ -730,8 +737,10 @@ __cxa_rethrow_primary_exception(void* th - dep_exception_header->unwindHeader.exception_cleanup = dependent_exception_cleanup; - #ifdef __USING_SJLJ_EXCEPTIONS__ - _Unwind_SjLj_RaiseException(&dep_exception_header->unwindHeader); -+#elif !LIBCXXABI_ARM_EHABI -+ _Unwind_RaiseException(&dep_exception_header->unwindHeader); - #else -- _Unwind_RaiseException(&dep_exception_header->unwindHeader); -+ _Unwind_RaiseException(dep_exception_header->unwindHeader); - #endif - // Some sort of unwinding error. Note that terminate is a handler. - __cxa_begin_catch(&dep_exception_header->unwindHeader); -Index: llvm-toolchain-snapshot_9~svn351647/libcxxabi/src/cxa_exception.hpp -=================================================================== ---- llvm-toolchain-snapshot_9~svn351647.orig/libcxxabi/src/cxa_exception.hpp -+++ llvm-toolchain-snapshot_9~svn351647/libcxxabi/src/cxa_exception.hpp -@@ -28,6 +28,45 @@ uint64_t __getExceptionClass (const _Un - void __setExceptionClass ( _Unwind_Exception*, uint64_t); - bool __isOurExceptionClass(const _Unwind_Exception*); - -+#if LIBCXXABI_ARM_EHABI -+// GCC has _Unwind_Control_Block in unwind.h (unwind_arm_common.h) -+#if defined(__clang__) -+struct _Unwind_Control_Block -+{ -+ uint64_t exception_class; -+ void (*exception_cleanup)(_Unwind_Reason_Code, _Unwind_Control_Block *); -+ struct { -+ _Unwind_Word reserved1; -+ _Unwind_Word reserved2; -+ _Unwind_Word reserved3; -+ _Unwind_Word reserved4; -+ _Unwind_Word reserved5; -+ } unwinder_cache; -+ struct { -+ _Unwind_Word sp; -+ _Unwind_Word bitpattern[5]; -+ } barrier_cache; -+ struct { -+ _Unwind_Word bitpattern[4]; -+ } cleanup_cache; -+ struct { -+ _Unwind_Word fnstart; -+ _Unwind_Word *ehtp; -+ _Unwind_Word additional; -+ _Unwind_Word reserved1; -+ } pr_cache; -+ long long int :0; -+ operator _Unwind_Exception*() noexcept -+ { -+ return reinterpret_cast<_Unwind_Exception*>(this); -+ } -+}; -+ -+#endif -+ -+#define _Unwind_Exception _Unwind_Control_Block -+#endif -+ - struct _LIBCXXABI_HIDDEN __cxa_exception { - #if defined(__LP64__) || defined(_LIBCXXABI_ARM_EHABI) - // This is a new field to support C++ 0x exception_ptr. diff --git a/debian/patches/libcxxabi-test-don-t-fail-extended-long-double.patch b/debian/patches/libcxxabi-test-don-t-fail-extended-long-double.patch deleted file mode 100644 index 7387d9e4..00000000 --- a/debian/patches/libcxxabi-test-don-t-fail-extended-long-double.patch +++ /dev/null @@ -1,17 +0,0 @@ -Powerpc has extended double that doesn't match x86 coding. Power format would -need special tests to verify correctness but for now it is enough to prevent -incorrect test from running. - -Index: llvm-toolchain-snapshot_9~svn351647/libcxxabi/test/test_demangle.pass.cpp -=================================================================== ---- llvm-toolchain-snapshot_9~svn351647.orig/libcxxabi/test/test_demangle.pass.cpp -+++ llvm-toolchain-snapshot_9~svn351647/libcxxabi/test/test_demangle.pass.cpp -@@ -29803,7 +29803,7 @@ const char* invalid_cases[] = - "NSoERj5E=Y1[uM:ga", - "Aon_PmKVPDk7?fg4XP5smMUL6;Vl<>IL8ayHpiVDDDXTY;^o9;i", - "_ZNSt16allocator_traitsISaIN4llvm3sys2fs18directory_iteratorEEE9constructIS3_IS3_EEEDTcl12_S_constructfp_fp0_spcl7forwardIT0_Efp1_EEERS4_PT_DpOS7_", --#if !LDBL_FP80 -+#if !LDBL_FP80 && __LDBL_MANT_DIG__ < 64 - "_ZN5test01hIfEEvRAcvjplstT_Le4001a000000000000000E_c", - #endif - // The following test cases were found by libFuzzer+ASAN diff --git a/debian/patches/llvm-riscv64-fix-cffi.diff b/debian/patches/llvm-riscv64-fix-cffi.diff new file mode 100644 index 00000000..61ba5759 --- /dev/null +++ b/debian/patches/llvm-riscv64-fix-cffi.diff @@ -0,0 +1,76 @@ +commit c6b09bff5671600f8e764d3847023d0996f328d9 +Author: Luís Marques +Date: Thu Nov 14 18:27:42 2019 +0000 + + [RISCV] Fix wrong CFI directives + + Summary: Removes CFI CFA directives that could incorrectly propagate + beyond the basic block they were inteded for. Specifically it removes + the epilogue CFI directives. See the branch_and_tail_call test for an + example of the issue. Should fix the stack unwinding issues caused by + the incorrect directives. + + Reviewers: asb, lenary, shiva0217 + Reviewed By: lenary + Tags: #llvm + Differential Revision: https://reviews.llvm.org/D69723 + +--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp ++++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +@@ -205,7 +205,6 @@ + MachineFrameInfo &MFI = MF.getFrameInfo(); + auto *RVFI = MF.getInfo(); + DebugLoc DL = MBBI->getDebugLoc(); +- const RISCVInstrInfo *TII = STI.getInstrInfo(); + unsigned FPReg = getFPReg(STI); + unsigned SPReg = getSPReg(STI); + +@@ -225,48 +224,9 @@ + adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset, + MachineInstr::FrameDestroy); + } +- +- if (hasFP(MF)) { +- // To find the instruction restoring FP from stack. +- for (auto &I = LastFrameDestroy; I != MBBI; ++I) { +- if (I->mayLoad() && I->getOperand(0).isReg()) { +- unsigned DestReg = I->getOperand(0).getReg(); +- if (DestReg == FPReg) { +- // If there is frame pointer, after restoring $fp registers, we +- // need adjust CFA to ($sp - FPOffset). +- // Emit ".cfi_def_cfa $sp, -FPOffset" +- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa( +- nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset)); +- BuildMI(MBB, std::next(I), DL, +- TII->get(TargetOpcode::CFI_INSTRUCTION)) +- .addCFIIndex(CFIIndex); +- break; +- } +- } +- } +- } +- +- // Add CFI directives for callee-saved registers. +- const std::vector &CSI = MFI.getCalleeSavedInfo(); +- // Iterate over list of callee-saved registers and emit .cfi_restore +- // directives. +- for (const auto &Entry : CSI) { +- unsigned Reg = Entry.getReg(); +- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore( +- nullptr, RI->getDwarfRegNum(Reg, true))); +- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) +- .addCFIIndex(CFIIndex); +- } + + // Deallocate stack + adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy); +- +- // After restoring $sp, we need to adjust CFA to $(sp + 0) +- // Emit ".cfi_def_cfa_offset 0" +- unsigned CFIIndex = +- MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0)); +- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) +- .addCFIIndex(CFIIndex); + } + + int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, diff --git a/debian/patches/no-z3.patch b/debian/patches/no-z3.patch new file mode 100644 index 00000000..8ebfd93a --- /dev/null +++ b/debian/patches/no-z3.patch @@ -0,0 +1,47 @@ +Description: + Disable z3 to avoid pulling ocaml into main. + For some reason the cmake option LLVM_ENABLE_Z3_SOLVER was not taken into account +Author: Gianfranco Costamagna + +Last-Update: 2019-11-26 + +Index: llvm-toolchain-9-9.0.0/llvm/CMakeLists.txt +=================================================================== +--- llvm-toolchain-9-9.0.0.orig/llvm/CMakeLists.txt ++++ llvm-toolchain-9-9.0.0/llvm/CMakeLists.txt +@@ -340,24 +340,22 @@ + + set(LLVM_Z3_INSTALL_DIR "" CACHE STRING "Install directory of the Z3 solver.") + +-find_package(Z3 4.7.1) +- +-if (LLVM_Z3_INSTALL_DIR) +- if (NOT Z3_FOUND) +- message(FATAL_ERROR "Z3 >= 4.7.1 has not been found in LLVM_Z3_INSTALL_DIR: ${LLVM_Z3_INSTALL_DIR}.") +- endif() +-endif() +- +-set(LLVM_ENABLE_Z3_SOLVER_DEFAULT "${Z3_FOUND}") +- + option(LLVM_ENABLE_Z3_SOLVER + "Enable Support for the Z3 constraint solver in LLVM." +- ${LLVM_ENABLE_Z3_SOLVER_DEFAULT} ++ ON + ) + + if (LLVM_ENABLE_Z3_SOLVER) +- if (NOT Z3_FOUND) +- message(FATAL_ERROR "LLVM_ENABLE_Z3_SOLVER cannot be enabled when Z3 is not available.") ++ find_package(Z3 4.7.1) ++ ++ if (LLVM_Z3_INSTALL_DIR) ++ if (NOT Z3_FOUND) ++ message(FATAL_ERROR "Z3 >= 4.7.1 has not been found in LLVM_Z3_INSTALL_DIR: ${LLVM_Z3_INSTALL_DIR}.") ++ endif() ++ else() ++ if (NOT Z3_FOUND) ++ message(FATAL_ERROR "LLVM_ENABLE_Z3_SOLVER cannot be enabled when Z3 is not available.") ++ endif() + endif() + + set(LLVM_WITH_Z3 1) diff --git a/debian/patches/revert-change-soname.diff b/debian/patches/revert-change-soname.diff deleted file mode 100644 index 24cca1ed..00000000 --- a/debian/patches/revert-change-soname.diff +++ /dev/null @@ -1,65 +0,0 @@ -Index: tools/llvm-shlib/simple_version_script.map.in -=================================================================== ---- tools/llvm-shlib/simple_version_script.map.in (revision 352580) -+++ tools/llvm-shlib/simple_version_script.map.in (revision 352579) -@@ -1 +1 @@ --LLVM_@LLVM_VERSION_MAJOR@.@LLVM_VERSION_MINOR@ { global: *; }; -+LLVM_@LLVM_VERSION_MAJOR@ { global: *; }; -Index: tools/llvm-config/CMakeLists.txt -=================================================================== ---- tools/llvm-config/CMakeLists.txt (revision 352580) -+++ tools/llvm-config/CMakeLists.txt (revision 352579) -@@ -37,7 +37,7 @@ - set(LLVM_CXXFLAGS "${CMAKE_CXX_FLAGS} ${CMAKE_CXX_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${COMPILE_FLAGS} ${LLVM_DEFINITIONS}") - set(LLVM_BUILD_SYSTEM cmake) - set(LLVM_HAS_RTTI ${LLVM_CONFIG_HAS_RTTI}) --set(LLVM_DYLIB_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}${LLVM_VERSION_SUFFIX}") -+set(LLVM_DYLIB_VERSION "${LLVM_VERSION_MAJOR}${LLVM_VERSION_SUFFIX}") - set(LLVM_HAS_GLOBAL_ISEL "ON") - - # Use the C++ link flags, since they should be a superset of C link flags. -Index: cmake/modules/AddLLVM.cmake -=================================================================== ---- cmake/modules/AddLLVM.cmake (revision 352580) -+++ cmake/modules/AddLLVM.cmake (revision 352579) -@@ -83,7 +83,7 @@ - # FIXME: Don't write the "local:" line on OpenBSD. - # in the export file, also add a linker script to version LLVM symbols (form: LLVM_N.M) - add_custom_command(OUTPUT ${native_export_file} -- COMMAND echo "LLVM_${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR} {" > ${native_export_file} -+ COMMAND echo "LLVM_${LLVM_VERSION_MAJOR} {" > ${native_export_file} - COMMAND grep -q "[[:alnum:]]" ${export_file} && echo " global:" >> ${native_export_file} || : - COMMAND sed -e "s/$/;/" -e "s/^/ /" < ${export_file} >> ${native_export_file} - COMMAND echo " local: *;" >> ${native_export_file} -@@ -500,7 +500,7 @@ - PROPERTIES - # Since 4.0.0, the ABI version is indicated by the major version - SOVERSION ${LLVM_VERSION_MAJOR} -- VERSION ${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}.${LLVM_VERSION_PATCH}${LLVM_VERSION_SUFFIX}) -+ VERSION ${LLVM_VERSION_MAJOR}${LLVM_VERSION_SUFFIX}) - endif() - endif() - -@@ -522,7 +522,7 @@ - if(${output_name} STREQUAL "output_name-NOTFOUND") - set(output_name ${name}) - endif() -- set(library_name ${output_name}-${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}${LLVM_VERSION_SUFFIX}) -+ set(library_name ${output_name}-${LLVM_VERSION_MAJOR}${LLVM_VERSION_SUFFIX}) - set(api_name ${output_name}-${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}.${LLVM_VERSION_PATCH}${LLVM_VERSION_SUFFIX}) - set_target_properties(${name} PROPERTIES OUTPUT_NAME ${library_name}) - llvm_install_library_symlink(${api_name} ${library_name} SHARED -Index: docs/ReleaseNotes.rst -=================================================================== ---- docs/ReleaseNotes.rst (revision 352580) -+++ docs/ReleaseNotes.rst (revision 352579) -@@ -30,6 +30,9 @@ - is available on the Visual Studio Marketplace. The new integration - supports Visual Studio 2017. - -+* Libraries have been renamed from 7.0 to 7. This change also impacts -+ downstream libraries like lldb. -+ - * The LoopInstSimplify pass (``-loop-instsimplify``) has been removed. - - * Symbols starting with ``?`` are no longer mangled by LLVM when using the diff --git a/debian/patches/series b/debian/patches/series index 9506f6b8..6336be16 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -125,6 +125,9 @@ bootstrap-fix-include-next.diff # riscv64 clang-riscv64-multiarch.diff +clang-riscv64-rv64gc.diff +llvm-riscv64-fix-cffi.diff +D60657-riscv-pcrel_lo.diff # Compiler-rt - workaround workaround-bug-42994-use-linker.diff @@ -133,3 +136,7 @@ workaround-bug-42994-use-linker.diff #try-to-unbreak-thinlto.diff D67877.patch disable-fuzzer-compiler-rt.diff +no-z3.patch + +# bug #946874 +D71028-mips-rust-test.diff diff --git a/debian/patches/try-to-unbreak-thinlto.diff b/debian/patches/try-to-unbreak-thinlto.diff deleted file mode 100644 index 5335566d..00000000 --- a/debian/patches/try-to-unbreak-thinlto.diff +++ /dev/null @@ -1,19 +0,0 @@ -Index: llvm-toolchain-9-9~+rc3/clang/CMakeLists.txt -=================================================================== ---- llvm-toolchain-9-9~+rc3.orig/clang/CMakeLists.txt -+++ llvm-toolchain-9-9~+rc3/clang/CMakeLists.txt -@@ -719,11 +719,9 @@ if (CLANG_ENABLE_BOOTSTRAP) - if(BOOTSTRAP_LLVM_ENABLE_LLD) - set(${CLANG_STAGE}_LINKER -DCMAKE_LINKER=${LLVM_RUNTIME_OUTPUT_INTDIR}/ld.lld) - endif() -- if(NOT BOOTSTRAP_LLVM_ENABLE_LTO) -- add_dependencies(clang-bootstrap-deps llvm-ar llvm-ranlib) -- set(${CLANG_STAGE}_AR -DCMAKE_AR=${LLVM_RUNTIME_OUTPUT_INTDIR}/llvm-ar) -- set(${CLANG_STAGE}_RANLIB -DCMAKE_RANLIB=${LLVM_RUNTIME_OUTPUT_INTDIR}/llvm-ranlib) -- endif() -+ add_dependencies(clang-bootstrap-deps llvm-ar llvm-ranlib) -+ set(${CLANG_STAGE}_AR -DCMAKE_AR=${LLVM_RUNTIME_OUTPUT_INTDIR}/llvm-ar) -+ set(${CLANG_STAGE}_RANLIB -DCMAKE_RANLIB=${LLVM_RUNTIME_OUTPUT_INTDIR}/llvm-ranlib) - add_dependencies(clang-bootstrap-deps llvm-objcopy llvm-strip) - set(${CLANG_STAGE}_OBJCOPY -DCMAKE_OBJCOPY=${LLVM_RUNTIME_OUTPUT_INTDIR}/llvm-objcopy) - set(${CLANG_STAGE}_STRIP -DCMAKE_STRIP=${LLVM_RUNTIME_OUTPUT_INTDIR}/llvm-strip) diff --git a/debian/python-lldb-X.Y.install.in b/debian/python-lldb-X.Y.install.in index 3e2c69ea..d74b8c35 100644 --- a/debian/python-lldb-X.Y.install.in +++ b/debian/python-lldb-X.Y.install.in @@ -1 +1 @@ -usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/site-packages/lldb/ +usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/*-packages/lldb/ diff --git a/debian/python-lldb-X.Y.links.in b/debian/python-lldb-X.Y.links.in index bce077f7..063bee37 100644 --- a/debian/python-lldb-X.Y.links.in +++ b/debian/python-lldb-X.Y.links.in @@ -1,6 +1,6 @@ -usr/lib/@DEB_HOST_MULTIARCH@/libLLVM-@LLVM_VERSION_FULL@.so.1 usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/site-packages/lldb/libLLVM-@LLVM_VERSION_FULL@.so.1 -usr/lib/@DEB_HOST_MULTIARCH@/libLLVM-@LLVM_VERSION_FULL@.so.1 usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/site-packages/lldb/libLLVM-@LLVM_VERSION@.so.1 -usr/lib/@DEB_HOST_MULTIARCH@/liblldb-@LLVM_VERSION@.so.1 usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/site-packages/lldb/_lldb.so +usr/lib/@DEB_HOST_MULTIARCH@/libLLVM-@LLVM_VERSION_FULL@.so.1 usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/dist-packages/lldb/libLLVM-@LLVM_VERSION_FULL@.so.1 +usr/lib/@DEB_HOST_MULTIARCH@/libLLVM-@LLVM_VERSION_FULL@.so.1 usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/dist-packages/lldb/libLLVM-@LLVM_VERSION@.so.1 +usr/lib/@DEB_HOST_MULTIARCH@/liblldb-@LLVM_VERSION@.so.1 usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/dist-packages/lldb/_lldb.so usr/lib/llvm-@LLVM_VERSION@/lib/python2.7/site-packages/lldb/ usr/lib/python2.7/dist-packages/lldb diff --git a/debian/qualify-clang.sh b/debian/qualify-clang.sh index 1ca071bd..f16c6c15 100755 --- a/debian/qualify-clang.sh +++ b/debian/qualify-clang.sh @@ -67,6 +67,19 @@ if ! grep -q -E "scan-build: 0 bugs found." foo.log; then fi rm -rf scan-build +echo 'namespace mozilla { +namespace dom { +void foo(); +} +} +' > foo.cpp +clang-tidy-$VERSION -checks='modernize-concat-nested-namespaces' foo.cpp -extra-arg=-std=c++17 &> foo.log +if ! grep -q "nested namespaces can " foo.log; then + echo "Clang-tidy didn't detect the issue" + cat foo.log + exit 1 +fi + echo "Testing clang-$VERSION ..." rm -f foo.log diff --git a/debian/rules b/debian/rules index f16ed770..9cbb0255 100755 --- a/debian/rules +++ b/debian/rules @@ -33,11 +33,7 @@ DISTRO=$(shell lsb_release -sc) DH_VERSION := $(shell dpkg -s debhelper | grep '^Version' | awk '{print $$2}') -DEB_HOST_MULTIARCH ?= $(shell dpkg-architecture -qDEB_HOST_MULTIARCH) -DEB_HOST_GNU_TYPE ?= $(shell dpkg-architecture -qDEB_HOST_GNU_TYPE) -DEB_HOST_ARCH_BITS ?= $(shell dpkg-architecture -qDEB_HOST_ARCH_BITS) -DEB_HOST_ARCH ?= $(shell dpkg-architecture -qDEB_HOST_ARCH) -DEB_HOST_ARCH_OS ?= $(shell dpkg-architecture -qDEB_HOST_ARCH_OS) +include /usr/share/dpkg/architecture.mk LDFLAGS_EXTRA = CXXFLAGS_EXTRA = @@ -70,11 +66,13 @@ ifeq ($(shell dpkg --compare-versions $(shell dpkg-query -W -f '$${Version}' g++ GCC_VERSION := 4.9 endif -Z3_FLAG= +Z3_FLAG = -DLLVM_ENABLE_Z3_SOLVER=OFF ifeq ($(shell dpkg --compare-versions $(shell dpkg-query -W -f '$${Version}' libz3-dev) gt 4.7.0; echo $$?),0) -# Too old version of gcc. Force 4.9 +# no ocaml support in main for Ubuntu +ifneq ($(shell dpkg-vendor --derives-from Ubuntu && echo yes),yes) Z3_FLAG = -DLLVM_ENABLE_Z3_SOLVER=ON endif +endif FORCE_NOT_GCC_9_DISTRO := eoan focal bullseye sid ifneq (,$(filter $(DISTRO),$(FORCE_NOT_GCC_9_DISTRO))) @@ -88,15 +86,7 @@ endif export CC=gcc-$(GCC_VERSION) export CXX=g++-$(GCC_VERSION) -opt_flags = -O2 -DNDEBUG - -# Only enable g1 on archs which needs it (it fixes an OOM during dh_strip due to huge symbols) -ifeq ($(DEB_HOST_ARCH_BITS),32) -opt_flags += -g1 -else -# Should be -g, but this causes buildd disk space issues -opt_flags += -g1 -endif +opt_flags = -O2 -DNDEBUG -g1 ifneq (,$(findstring $(DEB_HOST_ARCH),armel)) opt_flags += -marm @@ -386,7 +376,7 @@ override_dh_auto_configure: preconfigure -DCLANG_BUILD_EXAMPLES=OFF \ -DBOOTSTRAP_CMAKE_CXX_FLAGS='$(BOOTSTRAP_CXXFLAGS_EXTRA)' \ -DBOOTSTRAP_CMAKE_C_FLAGS='$(BOOTSTRAP_CFLAGS_EXTRA)' \ - -DCLANG_BOOTSTRAP_PASSTHROUGH="CMAKE_INSTALL_PREFIX;CMAKE_VERBOSE_MAKEFILE;CMAKE_BUILD_TYPE;CMAKE_CXX_FLAGS_RELWITHDEBINFO;LLVM_LINK_LLVM_DYLIB;LLVM_INSTALL_UTILS;LLVM_VERSION_SUFFIX;LLVM_ENABLE_SPHINX;SPHINX_WARNINGS_AS_ERRORS;LLVM_BUILD_LLVM_DYLIB;LLVM_ENABLE_RTTI;LLVM_ENABLE_FFI;LIBCLANG_LIBRARY_VERSION;ENABLE_LINKER_BUILD_ID;POLLY_BUNDLED_JSONCPP;LLVM_EXPERIMENTAL_TARGETS_TO_BUILD;LLVM_USE_PERF;LLVM_ENABLE_ASSERTIONS;LLVM_BINUTILS_INCDIR;LLVM_HOST_TRIPLE;;LLVM_COMPILER_CHECKED;COMPILER_RT_BUILD_BUILTINS;LIBOMP_LIBFLAGS;CMAKE_SHARED_LINKER_FLAGS;PYTHON_EXECUTABLE" + -DCLANG_BOOTSTRAP_PASSTHROUGH="CMAKE_INSTALL_PREFIX;CMAKE_VERBOSE_MAKEFILE;CMAKE_BUILD_TYPE;CMAKE_CXX_FLAGS_RELWITHDEBINFO;LLVM_LINK_LLVM_DYLIB;LLVM_INSTALL_UTILS;LLVM_VERSION_SUFFIX;LLVM_ENABLE_SPHINX;SPHINX_WARNINGS_AS_ERRORS;LLVM_BUILD_LLVM_DYLIB;LLVM_ENABLE_RTTI;LLVM_ENABLE_FFI;LIBCLANG_LIBRARY_VERSION;ENABLE_LINKER_BUILD_ID;POLLY_BUNDLED_JSONCPP;LLVM_EXPERIMENTAL_TARGETS_TO_BUILD;LLVM_USE_PERF;LLVM_ENABLE_ASSERTIONS;LLVM_BINUTILS_INCDIR;LLVM_HOST_TRIPLE;LLVM_COMPILER_CHECKED;COMPILER_RT_BUILD_BUILTINS;LIBOMP_LIBFLAGS;CMAKE_SHARED_LINKER_FLAGS;PYTHON_EXECUTABLE;LLVM_ENABLE_Z3_SOLVER" # make @@ -600,7 +590,7 @@ endif cp $(DEB_INST)/usr/lib/llvm-$(LLVM_VERSION)/lib/clang/$(LLVM_VERSION_FULL)/README.txt $(DEB_INST)/usr/lib/llvm-$(LLVM_VERSION)/lib/clang/$(LLVM_VERSION_FULL)/share/README.txt # idem for the lldb python binding - mkdir -p $(DEB_INST)/usr/lib/llvm-$(LLVM_VERSION)/lib/python2.7/site-packages/lldb/ + mkdir -p $(DEB_INST)/usr/lib/llvm-$(LLVM_VERSION)/lib/python2.7/dist-packages/lldb/ # Remove things that CMake install but which aren't packaged yet, # or are packaged from the source or build tree. @@ -664,7 +654,7 @@ endif sed -i 's|.*_IMPORT_CHECK_FILES_FOR_.*/bin/.*)|#&|' $(DEB_INST)/usr/lib/llvm-$(LLVM_VERSION)/lib/cmake/clang/ClangTargets-*.cmake # Managed in python-lldb-X.Y.links.in - rm -f $(DEB_INST)/usr/lib/llvm-$(LLVM_VERSION)/lib/python*/site-packages/lldb/_lldb.so + rm -f $(DEB_INST)/usr/lib/llvm-$(LLVM_VERSION)/lib/python*/*-packages/lldb/_lldb.so # Manage the polly files. Sometimes, we build them. Sometimes not. if test "$(POLLY_ENABLE)" = yes; then \ @@ -769,7 +759,7 @@ override_dh_installdeb: # Managed by the package dh_installdeb -a - rm -f $(CURDIR)/debian/tmp/usr/lib/llvm-$(LLVM_VERSION)/lib/python*/site-packages/lldb/__init__.pyc $(CURDIR)/debian/python-lldb-$(LLVM_VERSION)/usr/lib/llvm-$(LLVM_VERSION)/lib/python*/site-packages/lldb/__init__.pyc + rm -f $(CURDIR)/debian/tmp/usr/lib/llvm-$(LLVM_VERSION)/lib/python*/*-packages/lldb/__init__.pyc $(CURDIR)/debian/python-lldb-$(LLVM_VERSION)/usr/lib/llvm-$(LLVM_VERSION)/lib/python*/*-packages/lldb/__init__.pyc rm -f $(CURDIR)/debian/clang-$(LLVM_VERSION)-examples/usr/share/doc/clang-$(LLVM_VERSION)-examples/examples/*Make* # Remove auto generated python pyc @@ -813,7 +803,7 @@ endif ifeq (,$(filter $(DEB_HOST_ARCH), $(LLDB_DISABLE_ARCHS) armhf armel)) ifneq (,$(filter codecoverage,$(DEB_BUILD_OPTIONS))) # Create a symlink to run the testsuite: see https://bugs.archlinux.org/task/50759 - cd $(CURDIR)/$(TARGET_BUILD)/lib/python*/site-packages/; \ + cd $(CURDIR)/$(TARGET_BUILD)/lib/python*/*-packages/; \ if test ! -e _lldb.so; then \ ln -s lldb/_lldb.so; \ fi @@ -821,7 +811,7 @@ ifneq (,$(filter codecoverage,$(DEB_BUILD_OPTIONS))) LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(CURDIR)/$(TARGET_BUILD)/lib/ $(MAKE) $(NJOBS) -C $(TARGET_BUILD) check-lldb || true; \ fi # remove the workaround - rm $(CURDIR)/$(TARGET_BUILD)/lib/python*/site-packages/_lldb.so + rm $(CURDIR)/$(TARGET_BUILD)/lib/python*/*-packages/_lldb.so endif endif @@ -831,7 +821,7 @@ ifeq (${POLLY_ENABLE},yes) endif # Managed by debian build system - rm -f $(CURDIR)/$(TARGET_BUILD)/lib/python*/site-packages/lldb/_lldb.so + rm -f $(CURDIR)/$(TARGET_BUILD)/lib/python*/*-packages/lldb/_lldb.so # The compression of the code coverage report is done in the # hook B21GetCoverageResults on the server diff --git a/debian/source.lintian-overrides b/debian/source/lintian-overrides similarity index 100% rename from debian/source.lintian-overrides rename to debian/source/lintian-overrides diff --git a/debian/tests/cmake-test b/debian/tests/cmake-test index f63a5fd7..97f8bb2c 100755 --- a/debian/tests/cmake-test +++ b/debian/tests/cmake-test @@ -17,6 +17,7 @@ fi cd "$ADTTMP" cat < CMakeLists.txt cmake_minimum_required(VERSION 2.6.2) +project(cmake-test) find_package(LLVM 10.0.0 REQUIRED COMPONENTS Analysis diff --git a/debian/watch b/debian/watch index a372a166..a6d1751f 100644 --- a/debian/watch +++ b/debian/watch @@ -1,3 +1,3 @@ version=3 -http://llvm.org/releases/download.html .*/llvm-([\d\.\-]+).src.tar.xz +https://llvm.org/releases/download.html .*/llvm-([\d\.\-]+).src.tar.xz