From 2114e1f3157d0c6e9dfbc3851e6a1f3d27bacec0 Mon Sep 17 00:00:00 2001 From: Sylvestre Ledru Date: Thu, 9 Jun 2022 23:42:35 +0200 Subject: [PATCH 1/5] do not apply debian/patches//risc/riscv-insn-support.patch anymore as it doesn't apply on 14 --- debian/patches/series | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/patches/series b/debian/patches/series index f3874f74..df1661f8 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -116,7 +116,7 @@ bootstrap-fix-include-next.diff # riscv64 risc/clang-riscv64-multiarch.diff -risc/riscv-insn-support.patch +#risc/riscv-insn-support.patch # sparc64 D98574.patch From a83ccec7806ccff1863e31a0343a1c53ba218a30 Mon Sep 17 00:00:00 2001 From: Sylvestre Ledru Date: Sat, 11 Jun 2022 09:09:12 +0200 Subject: [PATCH 2/5] * New upstream release * Only install grpc files libclang-X.Y-dev when grpc built * autopkgtest: Restrict debian/qualify-clang.sh on amd64 arm64 i386 --- debian/changelog | 15 +++++++++++---- debian/tests/control | 1 + 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/debian/changelog b/debian/changelog index 362528ee..db89feae 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,14 +1,21 @@ -llvm-toolchain-14 (1:14.0.4-4) unstable; urgency=medium +llvm-toolchain-14 (1:14.0.5-1) unstable; urgency=medium + + * New upstream release + * Only install grpc files libclang-X.Y-dev when grpc built [ John Paul Adrian Glaubitz ] * Disable compiler-rt built-ins on x32 - [ Sylvestre Ledru ] - * Only install grpc files libclang-X.Y-dev when grpc built - [ Michael Biebl ] * Add support for systemd-binfmt (Closes: #1012368) + -- Sylvestre Ledru Sat, 11 Jun 2022 09:09:03 +0200 + +llvm-toolchain-14 (1:14.0.4-4) unstable; urgency=medium + + * autopkgtest: Restrict debian/qualify-clang.sh on + amd64 arm64 i386 + -- Sylvestre Ledru Fri, 03 Jun 2022 10:52:10 +0200 llvm-toolchain-14 (1:14.0.4-3) unstable; urgency=medium diff --git a/debian/tests/control b/debian/tests/control index cef87229..1818ce47 100644 --- a/debian/tests/control +++ b/debian/tests/control @@ -4,6 +4,7 @@ Depends: @, cmake, make, g++, file, dpkg-dev # dbgsym packages not being available in testing # clang-14-dbgsym, libclang1-14-dbgsym Restrictions: allow-stderr +Architecture: amd64 arm64 i386 Tests: integration-test-suite-test Depends: @, cmake, make, g++, libstdc++-10-dev From 0afa93c2422b114a376ffbf427fa56b99795d6b6 Mon Sep 17 00:00:00 2001 From: Sylvestre Ledru Date: Sat, 25 Jun 2022 09:56:35 +0200 Subject: [PATCH 3/5] * New upstream release * Remove cv-insn-support.patch (applied upstream) --- debian/changelog | 7 + debian/patches/risc/riscv-insn-support.patch | 566 ------------------- debian/patches/series | 1 - 3 files changed, 7 insertions(+), 567 deletions(-) delete mode 100644 debian/patches/risc/riscv-insn-support.patch diff --git a/debian/changelog b/debian/changelog index db89feae..2d801ef2 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,7 +1,14 @@ +llvm-toolchain-14 (1:14.0.6-1) unstable; urgency=medium + + * New upstream release + + -- Sylvestre Ledru Sat, 25 Jun 2022 09:56:23 +0200 + llvm-toolchain-14 (1:14.0.5-1) unstable; urgency=medium * New upstream release * Only install grpc files libclang-X.Y-dev when grpc built + * Remove cv-insn-support.patch (applied upstream) [ John Paul Adrian Glaubitz ] * Disable compiler-rt built-ins on x32 diff --git a/debian/patches/risc/riscv-insn-support.patch b/debian/patches/risc/riscv-insn-support.patch deleted file mode 100644 index 30283f6d..00000000 --- a/debian/patches/risc/riscv-insn-support.patch +++ /dev/null @@ -1,566 +0,0 @@ -From d5ea5842d627e63f780b524dddf67dac7222779c Mon Sep 17 00:00:00 2001 -From: Craig Topper -Date: Sun, 12 Sep 2021 13:45:52 -0700 -Origin: upstream + rustc: https://github.com/rust-lang/llvm-project/pull/121 -Bug-Ubuntu: https://bugs.launchpad.net/ubuntu/+source/llvm-toolchain-13/+bug/1973041 -Applied-Upstream: from version 14.0.0-rc1 -Subject: [PATCH] [RISCV] Initial support .insn directive for the assembler. - -This allows for a custom encoding to be emitted. It can also be -used with inline assembly to allow the custom instruction to be -register allocated like other instructions. - -I initially started from SystemZ's implementation, but some of -the formats allow operands to be specified in multiple ways so I -had to add support for matching different operand class lists for -the same format. That implementation is a simplified version of -what is emitted by tablegen for regular instructions. - -I've left out the compressed formats. And I haven't supported the -named opcodes like LUI or OP_IMM_32. Those can be added in future -patches. - -Documentation can be found here https://sourceware.org/binutils/docs-2.37/as/RISC_002dV_002dFormats.html - -Reviewed By: jrtc27, MaskRay - -Differential Revision: https://reviews.llvm.org/D108602 ---- - .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 63 ++++++++- - .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 5 +- - .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 2 +- - llvm/lib/Target/RISCV/RISCVInstrFormats.td | 132 ++++++++++++++++++ - llvm/lib/Target/RISCV/RISCVInstrInfo.td | 102 ++++++++++++++ - llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 12 ++ - llvm/test/MC/RISCV/insn-invalid.s | 17 +++ - llvm/test/MC/RISCV/insn.s | 77 ++++++++++ - 8 files changed, 407 insertions(+), 3 deletions(-) - create mode 100644 llvm/test/MC/RISCV/insn-invalid.s - create mode 100644 llvm/test/MC/RISCV/insn.s - -diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp -index 87496e0b9330f..ff2841a50d2d3 100644 ---- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp -+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp -@@ -169,6 +169,7 @@ class RISCVAsmParser : public MCTargetAsmParser { - - bool parseDirectiveOption(); - bool parseDirectiveAttribute(); -+ bool parseDirectiveInsn(SMLoc L); - - void setFeatureBits(uint64_t Feature, StringRef FeatureString) { - if (!(getSTI().getFeatureBits()[Feature])) { -@@ -504,6 +505,24 @@ struct RISCVOperand : public MCParsedAsmOperand { - return (isRV64() && isUInt<5>(Imm)) || isUInt<4>(Imm); - } - -+ bool isUImm2() const { -+ int64_t Imm; -+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; -+ if (!isImm()) -+ return false; -+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); -+ return IsConstantImm && isUInt<2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; -+ } -+ -+ bool isUImm3() const { -+ int64_t Imm; -+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; -+ if (!isImm()) -+ return false; -+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); -+ return IsConstantImm && isUInt<3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; -+ } -+ - bool isUImm5() const { - int64_t Imm; - RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; -@@ -513,6 +532,15 @@ struct RISCVOperand : public MCParsedAsmOperand { - return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; - } - -+ bool isUImm7() const { -+ int64_t Imm; -+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; -+ if (!isImm()) -+ return false; -+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); -+ return IsConstantImm && isUInt<7>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; -+ } -+ - bool isSImm5() const { - if (!isImm()) - return false; -@@ -1835,8 +1863,10 @@ bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { - - if (IDVal == ".option") - return parseDirectiveOption(); -- else if (IDVal == ".attribute") -+ if (IDVal == ".attribute") - return parseDirectiveAttribute(); -+ if (IDVal == ".insn") -+ return parseDirectiveInsn(DirectiveID.getLoc()); - - return true; - } -@@ -2200,6 +2230,37 @@ bool RISCVAsmParser::parseDirectiveAttribute() { - return false; - } - -+/// parseDirectiveInsn -+/// ::= .insn [ format encoding, (operands (, operands)*) ] -+bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) { -+ MCAsmParser &Parser = getParser(); -+ -+ // Expect instruction format as identifier. -+ StringRef Format; -+ SMLoc ErrorLoc = Parser.getTok().getLoc(); -+ if (Parser.parseIdentifier(Format)) -+ return Error(ErrorLoc, "expected instruction format"); -+ -+ if (Format != "r" && Format != "r4" && Format != "i" && Format != "b" && -+ Format != "sb" && Format != "u" && Format != "j" && Format != "uj" && -+ Format != "s") -+ return Error(ErrorLoc, "invalid instruction format"); -+ -+ std::string FormatName = (".insn_" + Format).str(); -+ -+ ParseInstructionInfo Info; -+ SmallVector, 8> Operands; -+ -+ if (ParseInstruction(Info, FormatName, L, Operands)) -+ return true; -+ -+ unsigned Opcode; -+ uint64_t ErrorInfo; -+ return MatchAndEmitInstruction(L, Opcode, Operands, Parser.getStreamer(), -+ ErrorInfo, -+ /*MatchingInlineAsm=*/false); -+} -+ - void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { - MCInst CInst; - bool Res = compressInst(CInst, Inst, getSTI(), S.getContext()); -diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h -index 9bdd2003cb15d..b837c4e25270b 100644 ---- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h -+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h -@@ -158,8 +158,11 @@ enum { - namespace RISCVOp { - enum OperandType : unsigned { - OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, -- OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM, -+ OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM, -+ OPERAND_UIMM3, -+ OPERAND_UIMM4, - OPERAND_UIMM5, -+ OPERAND_UIMM7, - OPERAND_UIMM12, - OPERAND_SIMM12, - OPERAND_UIMM20, -diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp -index 1ef276b101003..14d0191a505fc 100644 ---- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp -+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp -@@ -358,7 +358,7 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, - } - } else if (Kind == MCExpr::SymbolRef && - cast(Expr)->getKind() == MCSymbolRefExpr::VK_None) { -- if (Desc.getOpcode() == RISCV::JAL) { -+ if (MIFrm == RISCVII::InstFormatJ) { - FixupKind = RISCV::fixup_riscv_jal; - } else if (MIFrm == RISCVII::InstFormatB) { - FixupKind = RISCV::fixup_riscv_branch; -diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td -index 8e9d245f13eb0..944650c870b62 100644 ---- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td -+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td -@@ -406,3 +406,135 @@ class RVInstJ -+ : RVInst { -+ bits<7> opcode; -+ bits<7> funct7; -+ bits<3> funct3; -+ -+ bits<5> rs2; -+ bits<5> rs1; -+ bits<5> rd; -+ -+ let Inst{31-25} = funct7; -+ let Inst{24-20} = rs2; -+ let Inst{19-15} = rs1; -+ let Inst{14-12} = funct3; -+ let Inst{11-7} = rd; -+ let Opcode = opcode; -+ -+ let AsmString = ".insn r " # argstr; -+} -+ -+class DirectiveInsnR4 -+ : RVInst { -+ bits<7> opcode; -+ bits<2> funct2; -+ bits<3> funct3; -+ -+ bits<5> rs3; -+ bits<5> rs2; -+ bits<5> rs1; -+ bits<5> rd; -+ -+ let Inst{31-27} = rs3; -+ let Inst{26-25} = funct2; -+ let Inst{24-20} = rs2; -+ let Inst{19-15} = rs1; -+ let Inst{14-12} = funct3; -+ let Inst{11-7} = rd; -+ let Opcode = opcode; -+ -+ let AsmString = ".insn r4 " # argstr; -+} -+ -+class DirectiveInsnI -+ : RVInst { -+ bits<7> opcode; -+ bits<3> funct3; -+ -+ bits<12> imm12; -+ bits<5> rs1; -+ bits<5> rd; -+ -+ let Inst{31-20} = imm12; -+ let Inst{19-15} = rs1; -+ let Inst{14-12} = funct3; -+ let Inst{11-7} = rd; -+ let Opcode = opcode; -+ -+ let AsmString = ".insn i " # argstr; -+} -+ -+class DirectiveInsnS -+ : RVInst { -+ bits<7> opcode; -+ bits<3> funct3; -+ -+ bits<12> imm12; -+ bits<5> rs2; -+ bits<5> rs1; -+ -+ let Inst{31-25} = imm12{11-5}; -+ let Inst{24-20} = rs2; -+ let Inst{19-15} = rs1; -+ let Inst{14-12} = funct3; -+ let Inst{11-7} = imm12{4-0}; -+ let Opcode = opcode; -+ -+ let AsmString = ".insn s " # argstr; -+} -+ -+class DirectiveInsnB -+ : RVInst { -+ bits<7> opcode; -+ bits<3> funct3; -+ -+ bits<12> imm12; -+ bits<5> rs2; -+ bits<5> rs1; -+ -+ let Inst{31} = imm12{11}; -+ let Inst{30-25} = imm12{9-4}; -+ let Inst{24-20} = rs2; -+ let Inst{19-15} = rs1; -+ let Inst{14-12} = funct3; -+ let Inst{11-8} = imm12{3-0}; -+ let Inst{7} = imm12{10}; -+ let Opcode = opcode; -+ -+ let AsmString = ".insn b " # argstr; -+} -+ -+class DirectiveInsnU -+ : RVInst { -+ bits<7> opcode; -+ -+ bits<20> imm20; -+ bits<5> rd; -+ -+ let Inst{31-12} = imm20; -+ let Inst{11-7} = rd; -+ let Opcode = opcode; -+ -+ let AsmString = ".insn u " # argstr; -+} -+ -+class DirectiveInsnJ -+ : RVInst { -+ bits<7> opcode; -+ -+ bits<20> imm20; -+ bits<5> rd; -+ -+ let Inst{31-12} = imm20; -+ let Inst{11-7} = rd; -+ let Opcode = opcode; -+ -+ let AsmString = ".insn j " # argstr; -+} -diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td -index 949fff25e9e0a..1d6e4f04fce49 100644 ---- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td -+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td -@@ -152,6 +152,20 @@ def uimmlog2xlen : Operand, ImmLeaf { -+ let ParserMatchClass = UImmAsmOperand<2>; -+ let DecoderMethod = "decodeUImmOperand<2>"; -+ let OperandType = "OPERAND_UIMM2"; -+ let OperandNamespace = "RISCVOp"; -+} -+ -+def uimm3 : Operand { -+ let ParserMatchClass = UImmAsmOperand<3>; -+ let DecoderMethod = "decodeUImmOperand<3>"; -+ let OperandType = "OPERAND_UIMM3"; -+ let OperandNamespace = "RISCVOp"; -+} -+ - def uimm5 : Operand, ImmLeaf(Imm);}]> { - let ParserMatchClass = UImmAsmOperand<5>; - let DecoderMethod = "decodeUImmOperand<5>"; -@@ -159,6 +173,13 @@ def uimm5 : Operand, ImmLeaf(Imm);}]> { - let OperandNamespace = "RISCVOp"; - } - -+def uimm7 : Operand { -+ let ParserMatchClass = UImmAsmOperand<7>; -+ let DecoderMethod = "decodeUImmOperand<7>"; -+ let OperandType = "OPERAND_UIMM7"; -+ let OperandNamespace = "RISCVOp"; -+} -+ - def simm12 : Operand, ImmLeaf(Imm);}]> { - let ParserMatchClass = SImmAsmOperand<12>; - let EncoderMethod = "getImmOpValue"; -@@ -848,6 +869,87 @@ def : MnemonicAlias<"sbreak", "ebreak">; - // that don't support this alias. - def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>; - -+//===----------------------------------------------------------------------===// -+// .insn directive instructions -+//===----------------------------------------------------------------------===// -+ -+// isCodeGenOnly = 1 to hide them from the tablegened assembly parser. -+let isCodeGenOnly = 1, hasSideEffects = 1, mayLoad = 1, mayStore = 1, -+ hasNoSchedulingInfo = 1 in { -+def InsnR : DirectiveInsnR<(outs AnyReg:$rd), (ins uimm7:$opcode, uimm3:$funct3, -+ uimm7:$funct7, AnyReg:$rs1, -+ AnyReg:$rs2), -+ "$opcode, $funct3, $funct7, $rd, $rs1, $rs2">; -+def InsnR4 : DirectiveInsnR4<(outs AnyReg:$rd), (ins uimm7:$opcode, -+ uimm3:$funct3, -+ uimm2:$funct2, -+ AnyReg:$rs1, AnyReg:$rs2, -+ AnyReg:$rs3), -+ "$opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3">; -+def InsnI : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7:$opcode, uimm3:$funct3, -+ AnyReg:$rs1, simm12:$imm12), -+ "$opcode, $funct3, $rd, $rs1, $imm12">; -+def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7:$opcode, -+ uimm3:$funct3, -+ AnyReg:$rs1, -+ simm12:$imm12), -+ "$opcode, $funct3, $rd, ${imm12}(${rs1})">; -+def InsnB : DirectiveInsnB<(outs), (ins uimm7:$opcode, uimm3:$funct3, -+ AnyReg:$rs1, AnyReg:$rs2, -+ simm13_lsb0:$imm12), -+ "$opcode, $funct3, $rs1, $rs2, $imm12">; -+def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7:$opcode, -+ uimm20_lui:$imm20), -+ "$opcode, $rd, $imm20">; -+def InsnJ : DirectiveInsnJ<(outs AnyReg:$rd), (ins uimm7:$opcode, -+ simm21_lsb0_jal:$imm20), -+ "$opcode, $rd, $imm20">; -+def InsnS : DirectiveInsnS<(outs), (ins uimm7:$opcode, uimm3:$funct3, -+ AnyReg:$rs2, AnyReg:$rs1, -+ simm12:$imm12), -+ "$opcode, $funct3, $rs2, ${imm12}(${rs1})">; -+} -+ -+// Use InstAliases to match these so that we can combine the insn and format -+// into a mnemonic to use as the key for the tablegened asm matcher table. The -+// parser will take care of creating these fake mnemonics and will only do it -+// for known formats. -+let EmitPriority = 0 in { -+def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2", -+ (InsnR AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, -+ AnyReg:$rs1, AnyReg:$rs2)>; -+// Accept 4 register form of ".insn r" as alias for ".insn r4". -+def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2, $rs3", -+ (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, -+ AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>; -+def : InstAlias<".insn_r4 $opcode, $funct3, $funct7, $rd, $rs1, $rs2, $rs3", -+ (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, -+ AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>; -+def : InstAlias<".insn_i $opcode, $funct3, $rd, $rs1, $imm12", -+ (InsnI AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1, -+ simm12:$imm12)>; -+def : InstAlias<".insn_i $opcode, $funct3, $rd, ${imm12}(${rs1})", -+ (InsnI_Mem AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, -+ AnyReg:$rs1, simm12:$imm12)>; -+def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12", -+ (InsnB uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1, -+ AnyReg:$rs2, simm13_lsb0:$imm12)>; -+// Accept sb as an alias for b. -+def : InstAlias<".insn_sb $opcode, $funct3, $rs1, $rs2, $imm12", -+ (InsnB uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1, -+ AnyReg:$rs2, simm13_lsb0:$imm12)>; -+def : InstAlias<".insn_u $opcode, $rd, $imm20", -+ (InsnU AnyReg:$rd, uimm7:$opcode, uimm20_lui:$imm20)>; -+def : InstAlias<".insn_j $opcode, $rd, $imm20", -+ (InsnJ AnyReg:$rd, uimm7:$opcode, simm21_lsb0_jal:$imm20)>; -+// Accept uj as an alias for j. -+def : InstAlias<".insn_uj $opcode, $rd, $imm20", -+ (InsnJ AnyReg:$rd, uimm7:$opcode, simm21_lsb0_jal:$imm20)>; -+def : InstAlias<".insn_s $opcode, $funct3, $rs2, ${imm12}(${rs1})", -+ (InsnS uimm7:$opcode, uimm3:$funct3, AnyReg:$rs2, -+ AnyReg:$rs1, simm12:$imm12)>; -+} -+ - //===----------------------------------------------------------------------===// - // Pseudo-instructions and codegen patterns - // -diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td -index fde75206889c8..4dbeb61c48159 100644 ---- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td -+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td -@@ -557,3 +557,15 @@ foreach m = LMULList.m in { - def FFLAGS : RISCVReg<0, "fflags">; - def FRM : RISCVReg<0, "frm">; - def FCSR : RISCVReg<0, "fcsr">; -+ -+// Any type register. Used for .insn directives when we don't know what the -+// register types could be. -+// NOTE: The alignment and size are bogus values. The Size needs to be non-zero -+// or tablegen will use "untyped" to determine the size which will assert. -+let isAllocatable = 0 in -+def AnyReg : RegisterClass<"RISCV", [untyped], 32, -+ (add (sequence "X%u", 0, 31), -+ (sequence "F%u_D", 0, 31), -+ (sequence "V%u", 0, 31))> { -+ let Size = 32; -+} -diff --git a/llvm/test/MC/RISCV/insn-invalid.s b/llvm/test/MC/RISCV/insn-invalid.s -new file mode 100644 -index 0000000000000..5d7eaf69f01dc ---- /dev/null -+++ b/llvm/test/MC/RISCV/insn-invalid.s -@@ -0,0 +1,17 @@ -+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s -+ -+# Too many operands -+.insn i 0x13, 0, a0, a1, 13, 14 # CHECK: :[[@LINE]]:33: error: invalid operand for instruction -+.insn r 0x43, 0, 0, fa0, fa1, fa2, fa3, fa4 # CHECK: :[[@LINE]]:44: error: invalid operand for instruction -+ -+# Too few operands -+.insn r 0x33, 0, 0, a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -+.insn i 0x13, 0, a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -+ -+.insn r 0x33, 0, 0, a0, 13 # CHECK: :[[@LINE]]:28: error: invalid operand for instruction -+.insn i 0x13, 0, a0, a1, a2 # CHECK: :[[@LINE]]:28: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] -+ -+.insn q 0x13, 0, a0, a1, 13, 14 # CHECK: :[[@LINE]]:7: error: invalid instruction format -+ -+# Make fake mnemonics we use to match these in the tablegened asm match table isn't exposed. -+.insn_i 0x13, 0, a0, a1, 13, 14 # CHECK: :[[@LINE]]:1: error: unknown directive -diff --git a/llvm/test/MC/RISCV/insn.s b/llvm/test/MC/RISCV/insn.s -new file mode 100644 -index 0000000000000..1e02e22f965ad ---- /dev/null -+++ b/llvm/test/MC/RISCV/insn.s -@@ -0,0 +1,77 @@ -+# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases -show-encoding \ -+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s -+# RUN: llvm-mc %s -triple riscv64 -mattr=+f -riscv-no-aliases -show-encoding \ -+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s -+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+f < %s \ -+# RUN: | llvm-objdump --mattr=+f -M no-aliases -d -r - \ -+# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s -+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \ -+# RUN: | llvm-objdump --mattr=+f -M no-aliases -d -r - \ -+# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s -+ -+target: -+ -+# CHECK-ASM: .insn r 51, 0, 0, a0, a1, a2 -+# CHECK-ASM: encoding: [0x33,0x85,0xc5,0x00] -+# CHECK-OBJ: add a0, a1, a2 -+.insn r 0x33, 0, 0, a0, a1, a2 -+ -+# CHECK-ASM: .insn i 19, 0, a0, a1, 13 -+# CHECK-ASM: encoding: [0x13,0x85,0xd5,0x00] -+# CHECK-OBJ: addi a0, a1, 13 -+.insn i 0x13, 0, a0, a1, 13 -+ -+# CHECK-ASM: .insn i 103, 0, a0, 10(a1) -+# CHECK-ASM: encoding: [0x67,0x85,0xa5,0x00] -+# CHECK-OBJ: jalr a0, 10(a1) -+.insn i 0x67, 0, a0, 10(a1) -+ -+# CHECK-ASM: .insn i 3, 0, a0, 4(a1) -+# CHECK-ASM: encoding: [0x03,0x85,0x45,0x00] -+# CHECK-OBJ: lb a0, 4(a1) -+.insn i 0x3, 0, a0, 4(a1) -+ -+# CHECK-ASM: .insn b 99, 0, a0, a1, target -+# CHECK-ASM: [0x63'A',A,0xb5'A',A] -+# CHECK-OBJ: beq a0, a1, 0x0 -+.insn sb 0x63, 0, a0, a1, target -+ -+# CHECK-ASM: .insn b 99, 0, a0, a1, target -+# CHECK-ASM: [0x63'A',A,0xb5'A',A] -+# CHECK-OBJ: beq a0, a1, 0x0 -+.insn b 0x63, 0, a0, a1, target -+ -+# CHECK-ASM: .insn s 35, 0, a0, 4(a1) -+# CHECK-ASM: encoding: [0x23,0x82,0xa5,0x00] -+# CHECK-OBJ: sb a0, 4(a1) -+.insn s 0x23, 0, a0, 4(a1) -+ -+# CHECK-ASM: .insn u 55, a0, 4095 -+# CHECK-ASM: encoding: [0x37,0xf5,0xff,0x00] -+# CHECK-OBJ: lui a0, 4095 -+.insn u 0x37, a0, 0xfff -+ -+# CHECK-ASM: .insn j 111, a0, target -+# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A] -+# CHECK-OBJ: jal a0, 0x0 -+.insn uj 0x6f, a0, target -+ -+# CHECK-ASM: .insn j 111, a0, target -+# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A] -+# CHECK-OBJ: jal a0, 0x0 -+.insn j 0x6f, a0, target -+ -+# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3 -+# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68] -+# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne -+.insn r 0x43, 0, 0, fa0, fa1, fa2, fa3 -+ -+# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3 -+# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68] -+# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne -+.insn r4 0x43, 0, 0, fa0, fa1, fa2, fa3 -+ -+# CHECK-ASM: .insn i 3, 5, t1, -2048(t2) -+# CHECK-ASM: encoding: [0x03,0xd3,0x03,0x80] -+# CHECK-OBJ: lhu t1, -2048(t2) -+.insn i 0x3, 0x5, x6, %lo(2048)(x7) diff --git a/debian/patches/series b/debian/patches/series index df1661f8..a8251ea9 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -116,7 +116,6 @@ bootstrap-fix-include-next.diff # riscv64 risc/clang-riscv64-multiarch.diff -#risc/riscv-insn-support.patch # sparc64 D98574.patch From 75942c53c71bc57dc75650c9a9397455319b0b24 Mon Sep 17 00:00:00 2001 From: Sam McCall Date: Fri, 22 Jul 2022 13:08:40 +0000 Subject: [PATCH 4/5] Add symlink from /usr/include/c++/v1 -> /usr/lib/llvm-N/include/c++/v1 --- debian/changelog | 6 ++++++ debian/libc++-X.Y-dev.links.in | 1 + 2 files changed, 7 insertions(+) diff --git a/debian/changelog b/debian/changelog index be946006..10531a8c 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,9 @@ +llvm-toolchain-13 (1:13.0.1-8) UNRELEASED; urgency=medium + + * Add conventional symlink to libc++ headers in /usr/include/c++/v1 + + -- Sam McCall Fri, 22 Jul 2022 14:11:46 +0200 + llvm-toolchain-13 (1:13.0.1-7) UNRELEASED; urgency=medium * Add support for systemd-binfmt (Closes: #1012367) diff --git a/debian/libc++-X.Y-dev.links.in b/debian/libc++-X.Y-dev.links.in index 73efe8f5..90e84641 100644 --- a/debian/libc++-X.Y-dev.links.in +++ b/debian/libc++-X.Y-dev.links.in @@ -1,2 +1,3 @@ usr/lib/llvm-@LLVM_VERSION@/lib/libc++.so /usr/lib/x86_64-linux-gnu/libc++.so usr/lib/llvm-@LLVM_VERSION@/lib/libc++.a /usr/lib/x86_64-linux-gnu/libc++.a +usr/lib/llvm-@LLVM_VERSION@/include/c++/v1 /usr/include/c++/v1 From 85cc421c2092a8f7063f58d30cd3a5ad4108e69b Mon Sep 17 00:00:00 2001 From: Sylvestre Ledru Date: Fri, 22 Jul 2022 15:10:27 +0200 Subject: [PATCH 5/5] Improve the changelog --- debian/changelog | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/debian/changelog b/debian/changelog index 10531a8c..71a10603 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,14 +1,14 @@ -llvm-toolchain-13 (1:13.0.1-8) UNRELEASED; urgency=medium - - * Add conventional symlink to libc++ headers in /usr/include/c++/v1 - - -- Sam McCall Fri, 22 Jul 2022 14:11:46 +0200 - -llvm-toolchain-13 (1:13.0.1-7) UNRELEASED; urgency=medium +llvm-toolchain-13 (1:13.0.1-7) unstable; urgency=medium + [ Michael Biebl ] * Add support for systemd-binfmt (Closes: #1012367) - -- Michael Biebl Mon, 06 Jun 2022 01:19:25 +0200 + [ Sam McCall ] + * Add conventional symlink to libc++ headers in /usr/include/c++/v1 + See https://salsa.debian.org/pkg-llvm-team/llvm-toolchain/-/merge_requests/95 + for more information + + -- Sylvestre Ledru Fri, 22 Jul 2022 15:10:20 +0200 llvm-toolchain-13 (1:13.0.1-6) unstable; urgency=medium