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https://git.proxmox.com/git/llvm-toolchain
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* debian/patches/D158066.patch:
- upstream fix for Debian bug: #1049362
This commit is contained in:
Gianfranco Costamagna
parent
2c06d7deb9
commit
04b145d9b1
265
debian/patches/D158066.patch
vendored
Normal file
265
debian/patches/D158066.patch
vendored
Normal file
@ -0,0 +1,265 @@
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Description: Fix SIMD compatibility headers on ppc64el
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Origin/Author: https://reviews.llvm.org/D158066
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Bug-Debian: https://bugs.debian.org/1049362
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Index: llvm-toolchain-16-16.0.6/clang/include/clang/Basic/BuiltinsPPC.def
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===================================================================
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--- llvm-toolchain-16-16.0.6.orig/clang/include/clang/Basic/BuiltinsPPC.def
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+++ llvm-toolchain-16-16.0.6/clang/include/clang/Basic/BuiltinsPPC.def
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@@ -132,8 +132,10 @@
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BUILTIN(__builtin_ppc_extract_sig, "ULLid", "")
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BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
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BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
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+BUILTIN(__builtin_ppc_mffs, "d", "")
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BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
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BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
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+BUILTIN(__builtin_ppc_set_fpscr_rn, "di", "")
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BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "")
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BUILTIN(__builtin_ppc_fmsub, "dddd", "")
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BUILTIN(__builtin_ppc_fmsubs, "ffff", "")
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Index: llvm-toolchain-16-16.0.6/clang/lib/CodeGen/CGBuiltin.cpp
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===================================================================
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--- llvm-toolchain-16-16.0.6.orig/clang/lib/CodeGen/CGBuiltin.cpp
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+++ llvm-toolchain-16-16.0.6/clang/lib/CodeGen/CGBuiltin.cpp
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@@ -16742,6 +16742,11 @@
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Value *Op1 = EmitScalarExpr(E->getArg(1));
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return Builder.CreateFDiv(Op0, Op1, "swdiv");
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}
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+ case PPC::BI__builtin_ppc_set_fpscr_rn:
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+ return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_setrnd),
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+ {EmitScalarExpr(E->getArg(0))});
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+ case PPC::BI__builtin_ppc_mffs:
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+ return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_readflm));
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}
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}
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Index: llvm-toolchain-16-16.0.6/clang/lib/Headers/ppc_wrappers/smmintrin.h
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===================================================================
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--- llvm-toolchain-16-16.0.6.orig/clang/lib/Headers/ppc_wrappers/smmintrin.h
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+++ llvm-toolchain-16-16.0.6/clang/lib/Headers/ppc_wrappers/smmintrin.h
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@@ -14,7 +14,7 @@
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#ifndef NO_WARN_X86_INTRINSICS
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/* This header is distributed to simplify porting x86_64 code that
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- makes explicit use of Intel intrinsics to powerp64/powerpc64le.
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+ makes explicit use of Intel intrinsics to powerpc64/powerpc64le.
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It is the user's responsibility to determine if the results are
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acceptable and make additional changes as necessary.
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@@ -68,10 +68,10 @@
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__asm__("mffsce %0" : "=f"(__fpscr_save.__fr));
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__enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8;
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#else
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- __fpscr_save.__fr = __builtin_mffs();
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+ __fpscr_save.__fr = __builtin_ppc_mffs();
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__enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8;
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__fpscr_save.__fpscr &= ~0xf8;
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- __builtin_mtfsf(0b00000011, __fpscr_save.__fr);
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+ __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr);
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#endif
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/* Insert an artificial "read/write" reference to the variable
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read below, to ensure the compiler does not schedule
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@@ -83,10 +83,15 @@
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switch (__rounding) {
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case _MM_FROUND_TO_NEAREST_INT:
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- __fpscr_save.__fr = __builtin_mffsl();
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+#ifdef _ARCH_PWR9
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+ __fpscr_save.__fr = __builtin_ppc_mffsl();
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+#else
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+ __fpscr_save.__fr = __builtin_ppc_mffs();
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+ __fpscr_save.__fpscr &= 0x70007f0ffL;
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+#endif
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__attribute__((fallthrough));
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case _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC:
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- __builtin_set_fpscr_rn(0b00);
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+ __builtin_ppc_set_fpscr_rn(0b00);
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/* Insert an artificial "read/write" reference to the variable
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read below, to ensure the compiler does not schedule
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a read/use of the variable before the FPSCR is modified, above.
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@@ -102,7 +107,7 @@
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This can be removed if and when GCC PR102783 is fixed.
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*/
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__asm__("" : : "wa"(__r));
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- __builtin_set_fpscr_rn(__fpscr_save.__fpscr);
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+ __builtin_ppc_set_fpscr_rn(__fpscr_save.__fpscr);
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break;
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case _MM_FROUND_TO_NEG_INF:
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case _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC:
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@@ -128,9 +133,14 @@
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*/
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__asm__("" : : "wa"(__r));
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/* Restore enabled exceptions. */
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- __fpscr_save.__fr = __builtin_mffsl();
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+#ifdef _ARCH_PWR9
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+ __fpscr_save.__fr = __builtin_ppc_mffsl();
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+#else
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+ __fpscr_save.__fr = __builtin_ppc_mffs();
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+ __fpscr_save.__fpscr &= 0x70007f0ffL;
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+#endif
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__fpscr_save.__fpscr |= __enables_save.__fpscr;
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- __builtin_mtfsf(0b00000011, __fpscr_save.__fr);
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+ __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr);
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}
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return (__m128d)__r;
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}
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@@ -159,10 +169,10 @@
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__asm__("mffsce %0" : "=f"(__fpscr_save.__fr));
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__enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8;
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#else
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- __fpscr_save.__fr = __builtin_mffs();
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+ __fpscr_save.__fr = __builtin_ppc_mffs();
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__enables_save.__fpscr = __fpscr_save.__fpscr & 0xf8;
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__fpscr_save.__fpscr &= ~0xf8;
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- __builtin_mtfsf(0b00000011, __fpscr_save.__fr);
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+ __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr);
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#endif
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/* Insert an artificial "read/write" reference to the variable
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read below, to ensure the compiler does not schedule
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@@ -174,10 +184,15 @@
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switch (__rounding) {
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case _MM_FROUND_TO_NEAREST_INT:
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- __fpscr_save.__fr = __builtin_mffsl();
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+#ifdef _ARCH_PWR9
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+ __fpscr_save.__fr = __builtin_ppc_mffsl();
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+#else
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+ __fpscr_save.__fr = __builtin_ppc_mffs();
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+ __fpscr_save.__fpscr &= 0x70007f0ffL;
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+#endif
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__attribute__((fallthrough));
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case _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC:
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- __builtin_set_fpscr_rn(0b00);
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+ __builtin_ppc_set_fpscr_rn(0b00);
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/* Insert an artificial "read/write" reference to the variable
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read below, to ensure the compiler does not schedule
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a read/use of the variable before the FPSCR is modified, above.
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@@ -193,7 +208,7 @@
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This can be removed if and when GCC PR102783 is fixed.
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*/
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__asm__("" : : "wa"(__r));
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- __builtin_set_fpscr_rn(__fpscr_save.__fpscr);
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+ __builtin_ppc_set_fpscr_rn(__fpscr_save.__fpscr);
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break;
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case _MM_FROUND_TO_NEG_INF:
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case _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC:
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@@ -219,9 +234,14 @@
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*/
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__asm__("" : : "wa"(__r));
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/* Restore enabled exceptions. */
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- __fpscr_save.__fr = __builtin_mffsl();
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+#ifdef _ARCH_PWR9
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+ __fpscr_save.__fr = __builtin_ppc_mffsl();
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+#else
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+ __fpscr_save.__fr = __builtin_ppc_mffs();
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+ __fpscr_save.__fpscr &= 0x70007f0ffL;
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+#endif
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__fpscr_save.__fpscr |= __enables_save.__fpscr;
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- __builtin_mtfsf(0b00000011, __fpscr_save.__fr);
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+ __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr);
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}
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return (__m128)__r;
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}
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Index: llvm-toolchain-16-16.0.6/clang/test/CodeGen/PowerPC/builtins-ppc.c
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===================================================================
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--- llvm-toolchain-16-16.0.6.orig/clang/test/CodeGen/PowerPC/builtins-ppc.c
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+++ llvm-toolchain-16-16.0.6/clang/test/CodeGen/PowerPC/builtins-ppc.c
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@@ -1,5 +1,8 @@
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// REQUIRES: powerpc-registered-target
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-// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
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+// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - \
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+// RUN: | FileCheck %s
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+// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - \
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+// RUN: -target-cpu pwr9 | FileCheck %s --check-prefixes=P9,CHECK
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void test_eh_return_data_regno()
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{
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@@ -26,6 +29,9 @@
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// CHECK: call double @llvm.ppc.setrnd(i32 %2)
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res = __builtin_setrnd(x);
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+
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+ // CHECK: call double @llvm.ppc.setrnd(i32 %4)
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+ res = __builtin_ppc_set_fpscr_rn(x);
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}
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void test_builtin_ppc_flm() {
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@@ -33,7 +39,10 @@
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// CHECK: call double @llvm.ppc.readflm()
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res = __builtin_readflm();
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- // CHECK: call double @llvm.ppc.setflm(double %1)
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+ // CHECK: call double @llvm.ppc.readflm()
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+ res = __builtin_ppc_mffs();
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+
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+ // CHECK: call double @llvm.ppc.setflm(double %2)
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res = __builtin_setflm(res);
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}
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Index: llvm-toolchain-16-16.0.6/clang/test/CodeGen/PowerPC/ppc-smmintrin.c
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===================================================================
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--- llvm-toolchain-16-16.0.6.orig/clang/test/CodeGen/PowerPC/ppc-smmintrin.c
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+++ llvm-toolchain-16-16.0.6/clang/test/CodeGen/PowerPC/ppc-smmintrin.c
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@@ -239,44 +239,48 @@
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// CHECK-LABEL: @test_round
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// CHECK-LABEL: define available_externally <4 x float> @_mm_round_ps(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
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-// CHECK: call signext i32 @__builtin_mffs()
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-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
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+// CHECK: call double @llvm.ppc.readflm()
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+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
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// CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"
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-// CHECK: call signext i32 @__builtin_mffsl()
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-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i32 noundef signext 0)
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+// CHECK: call double @llvm.ppc.readflm()
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+// P10: call double @llvm.ppc.mffsl()
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+// CHECK: call double @llvm.ppc.setrnd(i32 0)
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// CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"
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// CHECK: call <4 x float> @vec_rint(float vector[4])
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// CHECK: call void asm sideeffect "", "^wa"
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-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i64 noundef %{{[0-9a-zA-Z_.]+}})
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+// CHECK: call double @llvm.ppc.setrnd(i32 %{{[0-9a-zA-Z_.]+}})
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// CHECK: call <4 x float> @vec_floor(float vector[4])
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// CHECK: call <4 x float> @vec_ceil(float vector[4])
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// CHECK: call <4 x float> @vec_trunc(float vector[4])
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// CHECK: call <4 x float> @vec_rint(float vector[4])
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// CHECK: call void asm sideeffect "", "^wa"
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-// CHECK: call signext i32 @__builtin_mffsl()
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-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
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+// CHECK: call double @llvm.ppc.readflm()
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+// P10: call double @llvm.ppc.mffsl()
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+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
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// CHECK-LABEL: define available_externally <4 x float> @_mm_round_ss(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, <4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
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// CHECK: call <4 x float> @_mm_round_ps(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
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// CHECK: extractelement <4 x float> %{{[0-9a-zA-Z_.]+}}, i32 0
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// CHECK-LABEL: define available_externally <2 x double> @_mm_round_pd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
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-// CHECK: call signext i32 @__builtin_mffs()
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-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
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+// CHECK: call double @llvm.ppc.readflm()
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+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
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// CHECK: %{{[0-9a-zA-Z_.]+}} = call <2 x double> asm "", "=^wa,0"
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-// CHECK: call signext i32 @__builtin_mffsl()
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-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i32 noundef signext 0)
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+// CHECK: call double @llvm.ppc.readflm()
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+// P10: call double @llvm.ppc.mffsl()
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+// CHECK: call double @llvm.ppc.setrnd(i32 0)
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// CHECK: %{{[0-9a-zA-Z_.]+}} = call <2 x double> asm "", "=^wa,0"
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// CHECK: call <2 x double> @vec_rint(double vector[2])
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// CHECK: call void asm sideeffect "", "^wa"
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-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i64 noundef %{{[0-9a-zA-Z_.]+}})
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+// CHECK: call double @llvm.ppc.setrnd(i32 %{{[0-9a-zA-Z_.]+}})
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// CHECK: call <2 x double> @vec_floor(double vector[2])
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// CHECK: call <2 x double> @vec_ceil(double vector[2])
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// CHECK: call <2 x double> @vec_trunc(double vector[2])
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// CHECK: call <2 x double> @vec_rint(double vector[2])
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// CHECK: call void asm sideeffect "", "^wa"
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-// CHECK: call signext i32 @__builtin_mffsl()
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-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
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+// CHECK: call double @llvm.ppc.readflm()
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+// P10: call double @llvm.ppc.mffsl()
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+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
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// CHECK-LABEL: define available_externally <2 x double> @_mm_round_sd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, <2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
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// CHECK: call <2 x double> @_mm_round_pd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
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1
debian/patches/series
vendored
1
debian/patches/series
vendored
@ -153,3 +153,4 @@ amdgpu/nonlinux.patch
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ubuntu-releases.patch
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new-cmake-build-fix.patch
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HIP-search-path-fix.patch
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D158066.patch
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