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121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/*
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* Copyright (C) 2018 Richard Hughes <richard@hughsie.com>
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*
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* SPDX-License-Identifier: LGPL-2.1+
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*/
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#pragma once
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#include <fwupdplugin.h>
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/* for all LDNs */
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#define SIO_LDNxx_IDX_LDNSEL 0x07
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#define SIO_LDNxx_IDX_CHIPID1 0x20
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#define SIO_LDNxx_IDX_CHIPID2 0x21
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#define SIO_LDNxx_IDX_CHIPVER 0x22
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#define SIO_LDNxx_IDX_SIOCTRL 0x23
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#define SIO_LDNxx_IDX_SIOIRQ 0x25
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#define SIO_LDNxx_IDX_SIOGP 0x26
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#define SIO_LDNxx_IDX_SIOPWR 0x2d
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#define SIO_LDNxx_IDX_D2ADR 0x2e
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#define SIO_LDNxx_IDX_D2DAT 0x2f
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#define SIO_LDNxx_IDX_IOBAD0 0x60 /* 16 bit */
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#define SIO_LDNxx_IDX_IOBAD1 0x62 /* 16 bit */
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/* these registers are only accessible by EC */
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#define GCTRL_ECHIPID1 0x2000
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#define GCTRL_ECHIPID2 0x2001
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#define GCTRL_ECHIPVER 0x2002
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/* to create sub-addresses */
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#define SIO_DEPTH2_I2EC_ADDRL 0x10
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#define SIO_DEPTH2_I2EC_ADDRH 0x11
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#define SIO_DEPTH2_I2EC_DATA 0x12
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/*
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* The PMC is a communication channel used between the host and the EC.
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* Compatible mode uses four registers:
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*
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* Name | EC | HOST | ADDR
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* _____________________|_______________|_______________|______
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* PMDIR | RO | WO | 0x62
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* PMDOR | WO | RO | 0x62
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* PMCMDR | RO | RO | 0x66
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* PMSTR | RO | RO | 0x66
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*/
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#define SIO_EC_PMC_PM1STS 0x00
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#define SIO_EC_PMC_PM1DO 0x01
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#define SIO_EC_PMC_PM1DOSCI 0x02
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#define SIO_EC_PMC_PM1DOCMI 0x03
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#define SIO_EC_PMC_PM1DI 0x04
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#define SIO_EC_PMC_PM1DISCI 0x05
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#define SIO_EC_PMC_PM1CTL 0x06
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#define SIO_EC_PMC_PM1IC 0x07
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#define SIO_EC_PMC_PM1IE 0x08
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/* SPI commands */
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#define SIO_SPI_CMD_READ 0x03
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#define SIO_SPI_CMD_HS_READ 0x0b
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#define SIO_SPI_CMD_FAST_READ_DUAL_OP 0x3b
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#define SIO_SPI_CMD_FAST_READ_DUAL_IO 0xbb
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#define SIO_SPI_CMD_4K_SECTOR_ERASE 0xd7 /* or 0x20 or 0x52 */
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#define SIO_SPI_CMD_64K_BLOCK_ERASE 0xd8
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#define SIO_SPI_CMD_CHIP_ERASE 0xc7 /* or 0x60 */
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#define SIO_SPI_CMD_PAGE_PROGRAM 0x02
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#define SIO_SPI_CMD_WRITE_WORD 0xad
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#define SIO_SPI_CMD_RDSR 0x05 /* read status register */
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#define SIO_SPI_CMD_WRSR 0x01 /* write status register */
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#define SIO_SPI_CMD_WREN 0x06 /* write enable */
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#define SIO_SPI_CMD_WRDI 0x04 /* write disable */
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#define SIO_SPI_CMD_RDID 0xab
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#define SIO_SPI_CMD_JEDEC_ID 0x9f
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#define SIO_SPI_CMD_DPD 0xb9 /* deep sleep */
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#define SIO_SPI_CMD_RDPD 0xab /* wake from deep sleep */
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/* EC Status Register (see ec/google/chromeec/ec_commands.h) */
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#define SIO_STATUS_EC_OBF (1 << 0) /* o/p buffer full */
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#define SIO_STATUS_EC_IBF (1 << 1) /* i/p buffer full */
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#define SIO_STATUS_EC_IS_BUSY (1 << 2)
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#define SIO_STATUS_EC_IS_CMD (1 << 3)
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#define SIO_STATUS_EC_BURST_ENABLE (1 << 4)
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#define SIO_STATUS_EC_SCI (1 << 5) /* 1 if more events in queue */
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/* EC Command Register (see KB3700-ds-01.pdf) */
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#define SIO_CMD_EC_READ 0x80
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#define SIO_CMD_EC_WRITE 0x81
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#define SIO_CMD_EC_BURST_ENABLE 0x82
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#define SIO_CMD_EC_BURST_DISABLE 0x83
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#define SIO_CMD_EC_QUERY_EVENT 0x84
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#define SIO_CMD_EC_GET_NAME_STR 0x92
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#define SIO_CMD_EC_GET_VERSION_STR 0x93
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#define SIO_CMD_EC_DISABLE_HOST_WA 0xdc
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#define SIO_CMD_EC_ENABLE_HOST_WA 0xfc
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typedef enum {
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SIO_LDN_FDC = 0x00, /* IT87 */
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SIO_LDN_UART1 = 0x01, /* IT87+IT89 */
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SIO_LDN_UART2 = 0x02, /* IT87+IT89 */
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SIO_LDN_PARALLEL_PORT = 0x03, /* IT87 */
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SIO_LDN_SWUC = 0x04, /* IT87+IT89 */
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SIO_LDN_KBC_MOUSE = 0x05, /* IT87+IT89 */
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SIO_LDN_KBC_KEYBOARD = 0x06, /* IT87+IT89 */
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SIO_LDN_GPIO = 0x07, /* IT87 */
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SIO_LDN_UART3 = 0x08, /* IT87 */
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SIO_LDN_UART4 = 0x09, /* IT87 */
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SIO_LDN_CIR = 0x0a, /* IT89 */
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SIO_LDN_SMFI = 0x0f, /* IT89 */
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SIO_LDN_RTCT = 0x10, /* IT89 */
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SIO_LDN_PM1 = 0x11, /* IT89 */
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SIO_LDN_PM2 = 0x12, /* IT89 */
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SIO_LDN_SSSP1 = 0x13, /* IT89 */
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SIO_LDN_PECI = 0x14, /* IT89 */
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SIO_LDN_PM3 = 0x17, /* IT89 */
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SIO_LDN_PM4 = 0x18, /* IT89 */
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SIO_LDN_PM5 = 0x19, /* IT89 */
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SIO_LDN_LAST = 0x1a
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} SioLdn;
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const gchar *
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fu_superio_ldn_to_text(guint8 ldn);
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