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af9d9b3ffd
Reset the CMOS based on a private flag. Tested on coreboot using an offset of 123. Required when a CMOS layout or default option has changed as the resulting flash will have 0's for the modified option.
56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
/*
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* Copyright (C) 2021 Sean Rhodes <sean@starlabs.systems>
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*
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* SPDX-License-Identifier: LGPL-2.1+
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*/
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#include "config.h"
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#include <sys/io.h>
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#include "fu-flashrom-cmos.h"
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static gboolean
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fu_flashrom_cmos_write(guint8 addr, guint8 val)
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{
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guint8 tmp;
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/* Reject addresses in the second bank */
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if (addr >= 128)
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return FALSE;
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/* Write the value to CMOS */
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outb(addr, RTC_BASE_PORT);
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outb(val, RTC_BASE_PORT + 1);
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/* Read the value back from CMOS */
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outb(addr, RTC_BASE_PORT);
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tmp = inb(RTC_BASE_PORT + 1);
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/* Check the read value against the written */
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return (tmp == val);
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}
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gboolean
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fu_flashrom_cmos_reset(GError **error)
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{
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/* Call ioperm() to grant us access to ports 0x70 and 0x71 */
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if (!ioperm(RTC_BASE_PORT, 2, TRUE)) {
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g_set_error_literal(error,
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FWUPD_ERROR,
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FWUPD_ERROR_READ,
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"failed to gain access to ports 0x70 and 0x71");
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return FALSE;
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}
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/* Write a default value to the CMOS checksum */
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if ((!fu_flashrom_cmos_write(CMOS_CHECKSUM_OFFSET, 0xff)) ||
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(!fu_flashrom_cmos_write(CMOS_CHECKSUM_OFFSET + 1, 0xff))) {
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g_set_error_literal(error, FWUPD_ERROR, FWUPD_ERROR_READ, "failed to reset CMOS");
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return FALSE;
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}
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/* success */
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return TRUE;
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}
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