mirror of
https://git.proxmox.com/git/fwupd
synced 2025-05-16 11:30:57 +00:00
81da69e73d
Correctly attach into the alternate mode after the update has completed. The vendor was appending two files to make LVFS distribution 'easier' but I'd much rather use the same deliverables as Windows. This also allows us to simplify the firmware loading.
373 lines
13 KiB
C
373 lines
13 KiB
C
/*
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* Copyright (C) 2020 Cypress Semiconductor Corporation.
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*
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* SPDX-License-Identifier: LGPL-2.1+
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*/
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#pragma once
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#include <glib.h>
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#define I2C_READ_WRITE_DELAY_US 10000 /* 10 msec */
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#define CY_SCB_INDEX_POS 15
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#define CY_I2C_WRITE_COMMAND_POS 3
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#define CY_I2C_WRITE_COMMAND_LEN_POS 4
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#define CY_I2C_GET_STATUS_LEN 3
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#define CY_I2C_MODE_WRITE 1
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#define CY_I2C_MODE_READ 0
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#define CY_I2C_ERROR_BIT 1
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#define CY_I2C_ARBITRATION_ERROR_BIT (1 << 1)
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#define CY_I2C_NAK_ERROR_BIT (1 << 2)
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#define CY_I2C_BUS_ERROR_BIT (1 << 3)
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#define CY_I2C_STOP_BIT_ERROR (1 << 4)
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#define CY_I2C_BUS_BUSY_ERROR (1 << 5)
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#define CY_I2C_ENABLE_PRECISE_TIMING 1
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#define CY_I2C_EVENT_NOTIFICATION_LEN 3
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#define PD_I2C_SLAVE_ADDRESS 0x08
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/* timeout (ms) for USB I2C communication */
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#define FU_CCGX_HPI_WAIT_TIMEOUT 5000
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/* max i2c frequency */
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#define FU_CCGX_HPI_FREQ 400000
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typedef enum {
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CY_GET_VERSION_CMD = 0xB0, /* get the version of the boot-loader
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* value = 0, index = 0, length = 4;
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* data_in = 32 bit version */
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CY_GET_SIGNATURE_CMD = 0xBD, /* get the signature of the firmware
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* It is suppose to be 'CYUS' for normal firmware
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* and 'CYBL' for Bootloader */
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CY_UART_GET_CONFIG_CMD = 0xC0, /* retreive the 16 byte UART configuration information
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* MS bit of value indicates the SCB index
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* length = 16, data_in = 16 byte configuration */
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CY_UART_SET_CONFIG_CMD, /* update the 16 byte UART configuration information
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* MS bit of value indicates the SCB index.
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* length = 16, data_out = 16 byte configuration information */
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CY_SPI_GET_CONFIG_CMD, /* retreive the 16 byte SPI configuration information
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* MS bit of value indicates the SCB index
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* length = 16, data_in = 16 byte configuration */
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CY_SPI_SET_CONFIG_CMD, /* update the 16 byte SPI configuration information
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* MS bit of value indicates the SCB index
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* length = 16, data_out = 16 byte configuration information */
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CY_I2C_GET_CONFIG_CMD, /* retreive the 16 byte I2C configuration information
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* MS bit of value indicates the SCB index
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* length = 16, data_in = 16 byte configuration */
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CY_I2C_SET_CONFIG_CMD = 0xC5, /* update the 16 byte I2C configuration information
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* MS bit of value indicates the SCB index
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* length = 16, data_out = 16 byte configuration information */
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CY_I2C_WRITE_CMD, /* perform I2C write operation
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* value = bit0 - start, bit1 - stop, bit3 - start on idle,
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* bits[14:8] - slave address, bit15 - scbIndex. length = 0 the
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* data is provided over the bulk endpoints */
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CY_I2C_READ_CMD, /* rerform I2C read operation.
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* value = bit0 - start, bit1 - stop, bit2 - Nak last byte,
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* bit3 - start on idle, bits[14:8] - slave address, bit15 - scbIndex,
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* length = 0. The data is provided over the bulk endpoints */
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CY_I2C_GET_STATUS_CMD, /* retreive the I2C bus status.
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* value = bit0 - 0: TX 1: RX, bit15 - scbIndex, length = 3,
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* data_in = byte0: bit0 - flag, bit1 - bus_state, bit2 - SDA state,
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* bit3 - TX underflow, bit4 - arbitration error, bit5 - NAK
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* bit6 - bus error,
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* byte[2:1] Data count remaining */
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CY_I2C_RESET_CMD, /* the command cleans up the I2C state machine and frees the bus
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* value = bit0 - 0: TX path, 1: RX path; bit15 - scbIndex,
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* length = 0 */
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CY_SPI_READ_WRITE_CMD = 0xCA, /* the command starts a read / write operation at SPI
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* value = bit 0 - RX enable, bit 1 - TX enable, bit 15 - scbIndex;
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* index = length of transfer */
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CY_SPI_RESET_CMD, /* the command resets the SPI pipes and allows it to receive new
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* request
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* value = bit 15 - scbIndex */
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CY_SPI_GET_STATUS_CMD, /* the command returns the current transfer status
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* the count will match the TX pipe status at SPI end
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* for completion of read, read all data
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* at the USB end signifies the end of transfer
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* value = bit 15 - scbIndex */
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CY_JTAG_ENABLE_CMD = 0xD0, /* enable JTAG module */
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CY_JTAG_DISABLE_CMD, /* disable JTAG module */
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CY_JTAG_READ_CMD, /* jtag read vendor command */
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CY_JTAG_WRITE_CMD, /* jtag write vendor command */
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CY_GPIO_GET_CONFIG_CMD = 0xD8, /* get the GPIO configuration */
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CY_GPIO_SET_CONFIG_CMD, /* set the GPIO configuration */
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CY_GPIO_GET_VALUE_CMD, /* get GPIO value */
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CY_GPIO_SET_VALUE_CMD, /* set the GPIO value */
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CY_PROG_USER_FLASH_CMD = 0xE0, /* program user flash area. The total space available is 512 bytes
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* this can be accessed by the user from USB. The flash area
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* address offset is from 0x0000 to 0x00200 and can be written to
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* page wise (128 byte) */
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CY_READ_USER_FLASH_CMD, /* read user flash area. The total space available is 512 bytes
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* this can be accessed by the user from USB. The flash area
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* address offset is from 0x0000 to 0x00200 and can be written to
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* page wise (128 byte) */
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CY_DEVICE_RESET_CMD = 0xE3, /* performs a device reset from firmware */
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} CyVendorCommand;
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typedef struct __attribute__((packed)) {
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guint32 frequency; /* frequency of operation. Only valid values are 100KHz and 400KHz */
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guint8 slave_address; /* slave address to be used when in slave mode */
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guint8 is_msb_first; /* whether to transmit most significant bit first */
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guint8 is_master; /* whether to block is to be configured as a master*/
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guint8 s_ignore; /* ignore general call in slave mode */
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guint8 is_clock_stretch; /* whether to stretch clock in case of no FIFO availability */
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guint8 is_loop_back; /* whether to loop back TX data to RX. Valid only for debug purposes */
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guint8 reserved[6];
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} CyI2CConfig;
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typedef enum {
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CY_I2C_DATA_CONFIG_NONE = 0,
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CY_I2C_DATA_CONFIG_STOP = 1 << 0,
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CY_I2C_DATA_CONFIG_NAK = 1 << 1, /* only for read */
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} CyI2CDataConfigBits;
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typedef enum {
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HPI_DEV_REG_DEVICE_MODE = 0,
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HPI_DEV_REG_BOOT_MODE_REASON,
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HPI_DEV_REG_SI_ID,
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HPI_DEV_REG_SI_ID_LSB,
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HPI_DEV_REG_BL_LAST_ROW,
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HPI_DEV_REG_BL_LAST_ROW_LSB,
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HPI_DEV_REG_INTR_ADDR,
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HPI_DEV_REG_JUMP_TO_BOOT,
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HPI_DEV_REG_RESET_ADDR,
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HPI_DEV_REG_RESET_CMD,
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HPI_DEV_REG_ENTER_FLASH_MODE,
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HPI_DEV_REG_VALIDATE_FW_ADDR,
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HPI_DEV_REG_FLASH_READ_WRITE,
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HPI_DEV_REG_FLASH_READ_WRITE_CMD,
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HPI_DEV_REG_FLASH_ROW,
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HPI_DEV_REG_FLASH_ROW_LSB,
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HPI_DEV_REG_ALL_VERSION,
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HPI_DEV_REG_ALL_VERSION_BYTE_1,
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HPI_DEV_REG_ALL_VERSION_BYTE_2,
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HPI_DEV_REG_ALL_VERSION_BYTE_3,
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HPI_DEV_REG_ALL_VERSION_BYTE_4,
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HPI_DEV_REG_ALL_VERSION_BYTE_5,
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HPI_DEV_REG_ALL_VERSION_BYTE_6,
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HPI_DEV_REG_ALL_VERSION_BYTE_7,
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HPI_DEV_REG_ALL_VERSION_BYTE_8,
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HPI_DEV_REG_ALL_VERSION_BYTE_9,
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HPI_DEV_REG_ALL_VERSION_BYTE_10,
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HPI_DEV_REG_ALL_VERSION_BYTE_11,
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HPI_DEV_REG_ALL_VERSION_BYTE_12,
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HPI_DEV_REG_ALL_VERSION_BYTE_13,
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HPI_DEV_REG_ALL_VERSION_BYTE_14,
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HPI_DEV_REG_ALL_VERSION_BYTE_15,
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HPI_DEV_REG_FW_2_VERSION,
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HPI_DEV_REG_FW_2_VERSION_BYTE_1,
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HPI_DEV_REG_FW_2_VERSION_BYTE_2,
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HPI_DEV_REG_FW_2_VERSION_BYTE_3,
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HPI_DEV_REG_FW_2_VERSION_BYTE_4,
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HPI_DEV_REG_FW_2_VERSION_BYTE_5,
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HPI_DEV_REG_FW_2_VERSION_BYTE_6,
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HPI_DEV_REG_FW_2_VERSION_BYTE_7,
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HPI_DEV_REG_FW_BIN_LOC,
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HPI_DEV_REG_FW_1_BIN_LOC_LSB,
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HPI_DEV_REG_FW_2_BIN_LOC_MSB,
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HPI_DEV_REG_FW_2_BIN_LOC_LSB,
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HPI_DEV_REG_PORT_ENABLE,
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HPI_DEV_SPACE_REG_LEN,
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HPI_DEV_REG_RESPONSE = 0x007E,
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HPI_DEV_REG_FLASH_MEM = 0x0200
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} HPIDevReg;
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typedef enum {
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HPI_REG_SECTION_DEV = 0, /* device information */
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HPI_REG_SECTION_PORT_0, /* USB-PD Port 0 related */
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HPI_REG_SECTION_PORT_1, /* USB-PD Port 1 related */
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HPI_REG_SECTION_ALL /* select all registers */
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} HPIRegSection;
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typedef struct __attribute__((packed)) {
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guint16 event_code;
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guint16 event_length;
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guint8 event_data[128];
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} HPIEvent;
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typedef enum {
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HPI_REG_PART_REG = 0, /* register region */
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HPI_REG_PART_DATA = 1, /* data memory */
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HPI_REG_PART_FLASH = 2, /* flash memory */
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HPI_REG_PART_PDDATA_READ = 4, /* read data memory */
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HPI_REG_PART_PDDATA_WRITE = 8, /* write data memory */
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} HPIRegPart;
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typedef enum {
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CY_PD_REG_DEVICE_MODE_ADDR,
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CY_PD_BOOT_MODE_REASON,
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CY_PD_SILICON_ID,
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CY_PD_BL_LAST_ROW = 0x04,
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CY_PD_REG_INTR_REG_ADDR = 0x06,
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CY_PD_JUMP_TO_BOOT_REG_ADDR,
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CY_PD_REG_RESET_ADDR,
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CY_PD_REG_ENTER_FLASH_MODE_ADDR = 0x0A,
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CY_PD_REG_VALIDATE_FW_ADDR,
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CY_PD_REG_FLASH_READ_WRITE_ADDR,
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CY_PD_GET_VERSION = 0x10,
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CY_PD_REG_DBG_PD_INIT = 0x12,
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CY_PD_REG_U_VDM_CTRL_ADDR = 0x20,
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CY_PD_REG_READ_PD_PROFILE = 0x22,
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CY_PD_REG_EFFECTIVE_SOURCE_PDO_MASK = 0x24,
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CY_PD_REG_EFFECTIVE_SINK_PDO_MASK,
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CY_PD_REG_SELECT_SOURCE_PDO,
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CY_PD_REG_SELECT_SINK_PDO,
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CY_PD_REG_PD_CONTROL,
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CY_PD_REG_PD_STATUS = 0x2C,
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CY_PD_REG_TYPE_C_STATUS = 0x30,
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CY_PD_REG_CURRENT_PDO = 0x34,
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CY_PD_REG_CURRENT_RDO = 0x38,
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CY_PD_REG_CURRENT_CABLE_VDO = 0x3C,
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CY_PD_REG_DISPLAY_PORT_STATUS = 0x40,
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CY_PD_REG_DISPLAY_PORT_CONFIG = 0x44,
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CY_PD_REG_ALTERNATE_MODE_MUX_SELECTION = 0X45,
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CY_PD_REG_EVENT_MASK = 0x48,
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CY_PD_REG_RESPONSE_ADDR = 0x7E,
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CY_PD_REG_BOOTDATA_MEMORY_ADDR = 0x80,
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CY_PD_REG_FWDATA_MEMEORY_ADDR = 0xC0,
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} CyPDReg;
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#define CY_PD_GET_SILICON_ID_CMD_SIG 0x53
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#define CY_PD_REG_INTR_REG_CLEAR_RQT 0x01
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#define CY_PD_JUMP_TO_BOOT_CMD_SIG 0x4A
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#define CY_PD_JUMP_TO_ALT_FW_CMD_SIG 0x41
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#define CY_PD_DEVICE_RESET_CMD_SIG 0x52
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#define CY_PD_REG_RESET_DEVICE_CMD 0x01
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#define CY_PD_ENTER_FLASHING_MODE_CMD_SIG 0x50
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#define CY_PD_FLASH_READ_WRITE_CMD_SIG 0x46
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#define CY_PD_REG_FLASH_ROW_READ_CMD 0x00
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#define CY_PD_REG_FLASH_ROW_WRITE_CMD 0x01
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#define CY_PD_REG_FLASH_READ_WRITE_ROW_LSB 0x02
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#define CY_PD_REG_FLASH_READ_WRITE_ROW_MSB 0x03
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#define CY_PD_U_VDM_TYPE 0x00
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#define HPI_GET_SILICON_ID_CMD_SIG 0x53
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#define HPI_REG_INTR_REG_CLEAR_RQT 0x01
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#define HPI_JUMP_TO_BOOT_CMD_SIG 0x4A
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#define HPI_DEVICE_RESET_CMD_SIG 0x52
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#define HPI_REG_RESET_DEVICE_CMD 0x01
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#define HPI_ENTER_FLASHING_MODE_CMD_SIG 0x50
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#define HPI_FLASH_READ_WRITE_CMD_SIG 0x46
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#define HPI_REG_FLASH_ROW_READ_CMD 0x00
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#define HPI_REG_FLASH_ROW_WRITE_CMD 0x01
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#define HPI_REG_FLASH_READ_WRITE_ROW_LSB 0x02
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#define HPI_REG_FLASH_READ_WRITE_ROW_MSB 0x03
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#define HPI_PORT_DISABLE_CMD 0x11
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#define HPI_DEVICE_VERSION_SIZE_HPIV1 16
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#define HPI_DEVICE_VERSION_SIZE_HPIV2 24
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#define HPI_META_DATA_OFFSET_ROW_128 64
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#define HPI_META_DATA_OFFSET_ROW_256 (64 + 128)
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#define PD_I2C_USB_EP_BULK_OUT 0x01
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#define PD_I2C_USB_EP_BULK_IN 0x82
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#define PD_I2C_USB_EP_INTR_IN 0x83
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#define PD_I2CM_USB_EP_BULK_OUT 0x02
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#define PD_I2CM_USB_EP_BULK_IN 0x83
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#define PD_I2CM_USB_EP_INTR_IN 0x84
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typedef enum {
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/* responses */
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CY_PD_RESP_NO_RESPONSE,
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CY_PD_RESP_SUCCESS = 0x02,
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CY_PD_RESP_FLASH_DATA_AVAILABLE,
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CY_PD_RESP_INVALID_COMMAND = 0x05,
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CY_PD_RESP_COLLISION_DETECTED,
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CY_PD_RESP_FLASH_UPDATE_FAILED,
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CY_PD_RESP_INVALID_FW,
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CY_PD_RESP_INVALID_ARGUMENTS,
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CY_PD_RESP_NOT_SUPPORTED,
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CY_PD_RESP_TRANSACTION_FAILED = 0x0C,
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CY_PD_RESP_PD_COMMAND_FAILED,
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CY_PD_RESP_UNDEFINED,
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CY_PD_RESP_RA_DETECT = 0x10,
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CY_PD_RESP_RA_REMOVED,
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/* device specific events */
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CY_PD_RESP_RESET_COMPLETE = 0x80,
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CY_PD_RESP_MESSAGE_QUEUE_OVERFLOW,
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/* type-c specific events */
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CY_PD_RESP_OVER_CURRENT_DETECTED,
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CY_PD_RESP_OVER_VOLTAGE_DETECTED,
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CY_PD_RESP_TYPC_C_CONNECTED,
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CY_PD_RESP_TYPE_C_DISCONNECTED,
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/* pd specific events and asynchronous messages */
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CY_PD_RESP_PD_CONTRACT_ESTABLISHED,
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CY_PD_RESP_DR_SWAP,
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CY_PD_RESP_PR_SWAP,
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CY_PD_RESP_VCON_SWAP,
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CY_PD_RESP_PS_RDY,
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CY_PD_RESP_GOTOMIN,
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CY_PD_RESP_ACCEPT_MESSAGE,
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CY_PD_RESP_REJECT_MESSAGE,
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CY_PD_RESP_WAIT_MESSAGE,
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CY_PD_RESP_HARD_RESET,
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CY_PD_RESP_VDM_RECEIVED,
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CY_PD_RESP_SRC_CAP_RCVD,
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CY_PD_RESP_SINK_CAP_RCVD,
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CY_PD_RESP_DP_ALTERNATE_MODE,
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CY_PD_RESP_DP_DEVICE_CONNECTED,
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CY_PD_RESP_DP_DEVICE_NOT_CONNECTED,
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CY_PD_RESP_DP_SID_NOT_FOUND,
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CY_PD_RESP_MULTIPLE_SVID_DISCOVERED,
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CY_PD_RESP_DP_FUNCTION_NOT_SUPPORTED,
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CY_PD_RESP_DP_PORT_CONFIG_NOT_SUPPORTED,
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CY_PD_HARD_RESET_SENT,
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CY_PD_SOFT_RESET_SENT,
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CY_PD_CABLE_RESET_SENT,
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CY_PD_SOURCE_DISBALED_STATE_ENTERED,
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CY_PD_SENDER_RESPONSE_TIMER_TIMEOUT,
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CY_PD_NO_VDM_RESPONSE_RECEIVED
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} CyPDResp;
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typedef enum {
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HPI_RESPONSE_NO_RESPONSE,
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HPI_RESPONSE_SUCCESS = 0x02,
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HPI_RESPONSE_FLASH_DATA_AVAILABLE,
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HPI_RESPONSE_INVALID_COMMAND = 0x05,
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HPI_RESPONSE_FLASH_UPDATE_FAILED = 0x07,
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HPI_RESPONSE_INVALID_FW,
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HPI_RESPONSE_INVALID_ARGUMENT,
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HPI_RESPONSE_NOT_SUPPORTED,
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HPI_RESPONSE_PD_TRANSACTION_FAILED = 0x0C,
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HPI_RESPONSE_PD_COMMAND_FAILED,
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HPI_RESPONSE_UNDEFINED_ERROR = 0x0F,
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HPI_EVENT_RESET_COMPLETE = 0x80,
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HPI_EVENT_MSG_OVERFLOW,
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HPI_EVENT_OC_DETECT,
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HPI_EVENT_OV_DETECT,
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HPI_EVENT_CONNECT_DETECT,
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HPI_EVENT_DISCONNECT_DETECT,
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HPI_EVENT_NEGOTIATION_COMPLETE,
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HPI_EVENT_SWAP_COMPLETE,
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HPI_EVENT_PS_RDY_RECEIVED = 0x8A,
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HPI_EVENT_GOTO_MIN_RECEIVED,
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HPI_EVENT_ACCEPT_RECEIVED,
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HPI_EVENT_REJECT_RECEIVED,
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HPI_EVENT_WAIT_RECEIVED,
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HPI_EVENT_HARD_RESET_RECEIVED,
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HPI_EVENT_VDM_RECEIVED = 0x90,
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HPI_EVENT_SOURCE_CAP_RECEIVED,
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HPI_EVENT_SINK_CAP_RECEIVED,
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HPI_EVENT_DP_MODE_ENTERED,
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HPI_EVENT_DP_STATUS_UPDATE,
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HPI_EVENT_DP_SID_NOT_FOUND = 0x96,
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HPI_EVENT_DP_MANY_SID_FOUND,
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HPI_EVENT_DP_NO_CABLE_SUPPORT,
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HPI_EVENT_DP_NO_UFP_SUPPORT,
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HPI_EVENT_HARD_RESET_SENT,
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HPI_EVENT_SOFT_RESET_SENT,
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HPI_EVENT_CABLE_RESET_SENT,
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HPI_EVENT_SOURCE_DISABLED,
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HPI_EVENT_SENDER_TIMEOUT,
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HPI_EVENT_VDM_NO_RESPONSE,
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HPI_EVENT_UNEXPECTED_VOLTAGE,
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HPI_EVENT_ERROR_RECOVERY,
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HPI_EVENT_EMCA_DETECT = 0xA6,
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HPI_EVENT_RP_CHANGE_DETECT = 0xAA,
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HPI_EVENT_TB_ENTERED = 0xB0,
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HPI_EVENT_TB_EXITED
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} HPIResp;
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