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af9d9b3ffd
Reset the CMOS based on a private flag. Tested on coreboot using an offset of 123. Required when a CMOS layout or default option has changed as the resulting flash will have 0's for the modified option.
23 lines
472 B
C
23 lines
472 B
C
/*
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* Copyright (C) 2021 Sean Rhodes <sean@starlabs.systems>
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*
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* SPDX-License-Identifier: LGPL-2.1+
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*/
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#pragma once
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#include <fwupdplugin.h>
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/* From coreboot's src/include/pc80/mc146818rtc.h file */
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#define RTC_BASE_PORT 0x70
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/*
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* This is the offset of the first of the two checksum bytes
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* we may want to figure out how we can determine this dynamically
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* during execution.
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*/
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#define CMOS_CHECKSUM_OFFSET 123
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gboolean
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fu_flashrom_cmos_reset(GError **error);
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