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f226350fcb
PR-URL: https://github.com/nodejs/node/pull/47251 Reviewed-By: Yagiz Nizipli <yagiz@nizipli.com> Reviewed-By: Jiawen Geng <technicalcute@gmail.com> Reviewed-By: Rafael Gonzaga <rafael.nunu@hotmail.com> Reviewed-By: Richard Lau <rlau@redhat.com>
240 lines
10 KiB
C++
240 lines
10 KiB
C++
// Copyright 2022 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#include "src/codegen/machine-type.h"
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#include "src/compiler/common-operator.h"
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#include "src/compiler/machine-graph.h"
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#include "src/compiler/machine-operator.h"
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#include "src/compiler/node-properties.h"
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#include "src/compiler/node.h"
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#include "src/compiler/revectorizer.h"
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#include "src/compiler/wasm-compiler.h"
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#include "src/wasm/wasm-module.h"
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#include "test/unittests/compiler/graph-unittest.h"
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#include "test/unittests/compiler/node-test-utils.h"
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#include "testing/gmock-support.h"
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using testing::AllOf;
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using testing::Capture;
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using testing::CaptureEq;
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namespace v8 {
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namespace internal {
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namespace compiler {
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class RevecTest : public TestWithIsolateAndZone {
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public:
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RevecTest()
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: TestWithIsolateAndZone(kCompressGraphZone),
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graph_(zone()),
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common_(zone()),
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machine_(zone(), MachineRepresentation::kWord64,
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MachineOperatorBuilder::Flag::kAllOptionalOps),
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mcgraph_(&graph_, &common_, &machine_) {}
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Graph* graph() { return &graph_; }
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CommonOperatorBuilder* common() { return &common_; }
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MachineOperatorBuilder* machine() { return &machine_; }
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MachineGraph* mcgraph() { return &mcgraph_; }
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private:
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Graph graph_;
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CommonOperatorBuilder common_;
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MachineOperatorBuilder machine_;
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MachineGraph mcgraph_;
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};
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// Create a graph which add two 256 bit vectors(a, b), store the result in c:
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// simd128 *a,*b,*c;
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// *c = *a + *b;
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// *(c+1) = *(a+1) + *(b+1);
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// In Revectorization, two simd 128 nodes can be combined into one 256 node:
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// simd256 *d, *e, *f;
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// *f = *d + *e;
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TEST_F(RevecTest, F32x8Add) {
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if (!CpuFeatures::IsSupported(AVX2)) return;
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Node* start = graph()->NewNode(common()->Start(5));
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graph()->SetStart(start);
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Node* zero = graph()->NewNode(common()->Int32Constant(0));
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Node* sixteen = graph()->NewNode(common()->Int64Constant(16));
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// offset of memory start field in WASM instance object.
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Node* offset = graph()->NewNode(common()->Int64Constant(23));
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Node* p0 = graph()->NewNode(common()->Parameter(0), start);
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Node* p1 = graph()->NewNode(common()->Parameter(1), start);
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Node* p2 = graph()->NewNode(common()->Parameter(2), start);
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Node* p3 = graph()->NewNode(common()->Parameter(3), start);
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StoreRepresentation store_rep(MachineRepresentation::kSimd128,
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WriteBarrierKind::kNoWriteBarrier);
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LoadRepresentation load_rep(MachineType::Simd128());
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Node* load0 = graph()->NewNode(machine()->Load(MachineType::Int64()), p0,
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offset, start, start);
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Node* mem_buffer1 = graph()->NewNode(machine()->Int64Add(), load0, sixteen);
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Node* mem_buffer2 = graph()->NewNode(machine()->Int64Add(), load0, sixteen);
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Node* mem_store = graph()->NewNode(machine()->Int64Add(), load0, sixteen);
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Node* load1 = graph()->NewNode(machine()->ProtectedLoad(load_rep), load0, p1,
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load0, start);
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Node* load2 = graph()->NewNode(machine()->ProtectedLoad(load_rep),
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mem_buffer1, p1, load1, start);
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Node* load3 = graph()->NewNode(machine()->ProtectedLoad(load_rep), load0, p2,
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load2, start);
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Node* load4 = graph()->NewNode(machine()->ProtectedLoad(load_rep),
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mem_buffer2, p2, load3, start);
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Node* add1 = graph()->NewNode(machine()->F32x4Add(), load1, load3);
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Node* add2 = graph()->NewNode(machine()->F32x4Add(), load2, load4);
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Node* store1 = graph()->NewNode(machine()->Store(store_rep), load0, p3, add1,
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load4, start);
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Node* store2 = graph()->NewNode(machine()->Store(store_rep), mem_store, p3,
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add2, store1, start);
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Node* ret = graph()->NewNode(common()->Return(0), zero, store2, start);
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Node* end = graph()->NewNode(common()->End(1), ret);
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graph()->SetEnd(end);
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graph()->RecordSimdStore(store1);
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graph()->RecordSimdStore(store2);
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graph()->SetSimd(true);
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// Test whether the graph can be revectorized
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Revectorizer revec(zone(), graph(), mcgraph());
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EXPECT_TRUE(revec.TryRevectorize(nullptr));
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// Test whether the graph has been revectorized
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Node* store_256 = ret->InputAt(1);
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EXPECT_EQ(StoreRepresentationOf(store_256->op()).representation(),
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MachineRepresentation::kSimd256);
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}
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// Create a graph which multiplies a F32x8 vector with the first element of
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// vector b and store the result to a F32x8 vector c:
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// float *a, *b, *c;
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// c[0123] = a[0123] * b[0000];
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// c[4567] = a[4567] * b[0000];
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//
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// After the revectorization phase, two consecutive 128-bit loads and multiplies
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// can be coalesced using 256-bit vectors:
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// c[01234567] = a[01234567] * b[00000000];
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TEST_F(RevecTest, F32x8Mul) {
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if (!CpuFeatures::IsSupported(AVX2)) return;
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Node* start = graph()->NewNode(common()->Start(4));
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graph()->SetStart(start);
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Node* zero = graph()->NewNode(common()->Int32Constant(0));
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Node* sixteen = graph()->NewNode(common()->Int64Constant(16));
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Node* offset = graph()->NewNode(common()->Int64Constant(23));
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// Wasm array base address
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Node* p0 = graph()->NewNode(common()->Parameter(0), start);
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// Load base address a*
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Node* p1 = graph()->NewNode(common()->Parameter(1), start);
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// LoadTransfrom base address b*
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Node* p2 = graph()->NewNode(common()->Parameter(2), start);
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// Store base address c*
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Node* p3 = graph()->NewNode(common()->Parameter(3), start);
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LoadRepresentation load_rep(MachineType::Simd128());
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StoreRepresentation store_rep(MachineRepresentation::kSimd128,
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WriteBarrierKind::kNoWriteBarrier);
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Node* base = graph()->NewNode(machine()->Load(MachineType::Int64()), p0,
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offset, start, start);
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Node* base16 = graph()->NewNode(machine()->Int64Add(), base, sixteen);
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Node* base16_store = graph()->NewNode(machine()->Int64Add(), base, sixteen);
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Node* load0 = graph()->NewNode(machine()->ProtectedLoad(load_rep), base, p1,
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base, start);
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Node* load1 = graph()->NewNode(machine()->ProtectedLoad(load_rep), base16, p1,
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load0, start);
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Node* load2 = graph()->NewNode(
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machine()->LoadTransform(MemoryAccessKind::kProtected,
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LoadTransformation::kS128Load32Splat),
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base, p2, load1, start);
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Node* mul0 = graph()->NewNode(machine()->F32x4Mul(), load0, load2);
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Node* mul1 = graph()->NewNode(machine()->F32x4Mul(), load1, load2);
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Node* store0 = graph()->NewNode(machine()->Store(store_rep), base, p3, mul0,
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load2, start);
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Node* store1 = graph()->NewNode(machine()->Store(store_rep), base16_store, p3,
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mul1, store0, start);
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Node* ret = graph()->NewNode(common()->Return(0), zero, store1, start);
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Node* end = graph()->NewNode(common()->End(1), ret);
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graph()->SetEnd(end);
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graph()->RecordSimdStore(store0);
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graph()->RecordSimdStore(store1);
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graph()->SetSimd(true);
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Revectorizer revec(zone(), graph(), mcgraph());
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EXPECT_TRUE(revec.TryRevectorize(nullptr));
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// Test whether the graph has been revectorized
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Node* store_256 = ret->InputAt(1);
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EXPECT_EQ(StoreRepresentationOf(store_256->op()).representation(),
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MachineRepresentation::kSimd256);
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}
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// Create a graph with load chain that can not be packed due to effect
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// dependency:
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// [Load4] -> [Load3] -> [Load2] -> [Irrelevant Load] -> [Load1]
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//
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// After reordering, no effect dependency will be broken so the graph can be
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// revectorized:
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// [Load4] -> [Load3] -> [Load2] -> [Load1] -> [Irrelevant Load]
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TEST_F(RevecTest, ReorderLoadChain) {
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if (!CpuFeatures::IsSupported(AVX2)) return;
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Node* start = graph()->NewNode(common()->Start(5));
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graph()->SetStart(start);
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Node* zero = graph()->NewNode(common()->Int32Constant(0));
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Node* sixteen = graph()->NewNode(common()->Int64Constant(16));
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// offset of memory start field in WASM instance object.
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Node* offset = graph()->NewNode(common()->Int64Constant(23));
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Node* p0 = graph()->NewNode(common()->Parameter(0), start);
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Node* p1 = graph()->NewNode(common()->Parameter(1), start);
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Node* p2 = graph()->NewNode(common()->Parameter(2), start);
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Node* p3 = graph()->NewNode(common()->Parameter(3), start);
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StoreRepresentation store_rep(MachineRepresentation::kSimd128,
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WriteBarrierKind::kNoWriteBarrier);
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LoadRepresentation load_rep(MachineType::Simd128());
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Node* load0 = graph()->NewNode(machine()->Load(MachineType::Int64()), p0,
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offset, start, start);
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Node* mem_buffer1 = graph()->NewNode(machine()->Int64Add(), load0, sixteen);
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Node* mem_buffer2 = graph()->NewNode(machine()->Int64Add(), load0, sixteen);
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Node* mem_store = graph()->NewNode(machine()->Int64Add(), load0, sixteen);
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Node* load1 = graph()->NewNode(machine()->ProtectedLoad(load_rep), load0, p1,
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load0, start);
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Node* irrelevant_load = graph()->NewNode(machine()->ProtectedLoad(load_rep),
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mem_buffer1, p1, load1, start);
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Node* load2 = graph()->NewNode(machine()->ProtectedLoad(load_rep),
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mem_buffer1, p1, irrelevant_load, start);
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Node* load3 = graph()->NewNode(machine()->ProtectedLoad(load_rep), load0, p2,
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load2, start);
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Node* load4 = graph()->NewNode(machine()->ProtectedLoad(load_rep),
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mem_buffer2, p2, load3, start);
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Node* add1 = graph()->NewNode(machine()->F32x4Add(), load1, load3);
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Node* add2 = graph()->NewNode(machine()->F32x4Add(), load2, load4);
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Node* store1 = graph()->NewNode(machine()->Store(store_rep), load0, p3, add1,
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load4, start);
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Node* store2 = graph()->NewNode(machine()->Store(store_rep), mem_store, p3,
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add2, store1, start);
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Node* ret = graph()->NewNode(common()->Return(0), zero, store2, start);
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Node* end = graph()->NewNode(common()->End(1), ret);
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graph()->SetEnd(end);
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graph()->RecordSimdStore(store1);
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graph()->RecordSimdStore(store2);
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graph()->SetSimd(true);
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// Test whether the graph can be revectorized
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Revectorizer revec(zone(), graph(), mcgraph());
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EXPECT_TRUE(revec.TryRevectorize(nullptr));
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}
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} // namespace compiler
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} // namespace internal
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} // namespace v8
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