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c8c0d267fd
This includes definitions of various basic parameters needed for integration of a new platform into QEMU. [AM: Split a larger AVR introduction patch into logical units] Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Co-developed-by: Michael Rolnik <mrolnik@gmail.com> Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [thuth: Simplify MAINTAINERS right from the start] Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-2-huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
/*
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* QEMU AVR CPU
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*
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* Copyright (c) 2016-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef AVR_CPU_PARAM_H
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#define AVR_CPU_PARAM_H
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#define TARGET_LONG_BITS 32
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/*
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* TARGET_PAGE_BITS cannot be more than 8 bits because
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* 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they
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* should be implemented as a device and not memory
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* 2. SRAM starts at the address 0x0100
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*/
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#define TARGET_PAGE_BITS 8
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#define TARGET_PHYS_ADDR_SPACE_BITS 24
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#define TARGET_VIRT_ADDR_SPACE_BITS 24
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#define NB_MMU_MODES 2
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#endif
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