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There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122913.19561-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
282 lines
9.4 KiB
Plaintext
282 lines
9.4 KiB
Plaintext
# Thumb1 instructions
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#
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# Copyright (c) 2019 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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&empty !extern
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&s_rrr_shi !extern s rd rn rm shim shty
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&s_rrr_shr !extern s rn rd rm rs shty
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&s_rri_rot !extern s rn rd imm rot
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&s_rrrr !extern s rd rn rm ra
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&rrr_rot !extern rd rn rm rot
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&rr !extern rd rm
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&ri !extern rd imm
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&r !extern rm
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&i !extern imm
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&ldst_rr !extern p w u rn rt rm shimm shtype
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&ldst_ri !extern p w u rn rt imm
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&ldst_block !extern rn i b u w list
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&setend !extern E
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&cps !extern mode imod M A I F
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&ci !extern cond imm
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# Set S if the instruction is outside of an IT block.
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%s !function=t16_setflags
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# Data-processing (two low registers)
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%reg_0 0:3
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@lll_noshr ...... .... rm:3 rd:3 \
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&s_rrr_shi %s rn=%reg_0 shim=0 shty=0
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@xll_noshr ...... .... rm:3 rn:3 \
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&s_rrr_shi s=1 rd=0 shim=0 shty=0
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@lxl_shr ...... .... rs:3 rd:3 \
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&s_rrr_shr %s rm=%reg_0 rn=0
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AND_rrri 010000 0000 ... ... @lll_noshr
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EOR_rrri 010000 0001 ... ... @lll_noshr
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MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
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MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
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MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
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ADC_rrri 010000 0101 ... ... @lll_noshr
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SBC_rrri 010000 0110 ... ... @lll_noshr
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MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
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TST_xrri 010000 1000 ... ... @xll_noshr
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RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
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CMP_xrri 010000 1010 ... ... @xll_noshr
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CMN_xrri 010000 1011 ... ... @xll_noshr
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ORR_rrri 010000 1100 ... ... @lll_noshr
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MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
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BIC_rrri 010000 1110 ... ... @lll_noshr
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MVN_rxri 010000 1111 ... ... @lll_noshr
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# Load/store (register offset)
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@ldst_rr ....... rm:3 rn:3 rt:3 \
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&ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
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STR_rr 0101 000 ... ... ... @ldst_rr
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STRH_rr 0101 001 ... ... ... @ldst_rr
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STRB_rr 0101 010 ... ... ... @ldst_rr
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LDRSB_rr 0101 011 ... ... ... @ldst_rr
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LDR_rr 0101 100 ... ... ... @ldst_rr
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LDRH_rr 0101 101 ... ... ... @ldst_rr
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LDRB_rr 0101 110 ... ... ... @ldst_rr
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LDRSH_rr 0101 111 ... ... ... @ldst_rr
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# Load/store word/byte (immediate offset)
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%imm5_6x4 6:5 !function=times_4
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@ldst_ri_1 ..... imm:5 rn:3 rt:3 \
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&ldst_ri p=1 w=0 u=1
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@ldst_ri_4 ..... ..... rn:3 rt:3 \
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&ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
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STR_ri 01100 ..... ... ... @ldst_ri_4
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LDR_ri 01101 ..... ... ... @ldst_ri_4
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STRB_ri 01110 ..... ... ... @ldst_ri_1
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LDRB_ri 01111 ..... ... ... @ldst_ri_1
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# Load/store halfword (immediate offset)
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%imm5_6x2 6:5 !function=times_2
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@ldst_ri_2 ..... ..... rn:3 rt:3 \
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&ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
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STRH_ri 10000 ..... ... ... @ldst_ri_2
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LDRH_ri 10001 ..... ... ... @ldst_ri_2
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# Load/store (SP-relative)
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%imm8_0x4 0:8 !function=times_4
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@ldst_spec_i ..... rt:3 ........ \
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&ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
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STR_ri 10010 ... ........ @ldst_spec_i rn=13
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LDR_ri 10011 ... ........ @ldst_spec_i rn=13
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# Load (PC-relative)
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LDR_ri 01001 ... ........ @ldst_spec_i rn=15
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# Add PC/SP (immediate)
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ADR 10100 rd:3 ........ imm=%imm8_0x4
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ADD_rri 10101 rd:3 ........ \
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&s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
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# Load/store multiple
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@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1
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STM 11000 ... ........ @ldstm
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LDM_t16 11001 ... ........ @ldstm
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# Shift (immediate)
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@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0
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MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
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MOV_rxri 000 01 ..... ... ... @shift_i shty=1 # LSR
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MOV_rxri 000 10 ..... ... ... @shift_i shty=2 # ASR
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# Add/subtract (three low registers)
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@addsub_3 ....... rm:3 rn:3 rd:3 \
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&s_rrr_shi %s shim=0 shty=0
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ADD_rrri 0001100 ... ... ... @addsub_3
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SUB_rrri 0001101 ... ... ... @addsub_3
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# Add/subtract (two low registers and immediate)
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@addsub_2i ....... imm:3 rn:3 rd:3 \
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&s_rri_rot %s rot=0
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ADD_rri 0001 110 ... ... ... @addsub_2i
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SUB_rri 0001 111 ... ... ... @addsub_2i
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# Add, subtract, compare, move (one low register and immediate)
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%reg_8 8:3
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@arith_1i ..... rd:3 imm:8 \
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&s_rri_rot rot=0 rn=%reg_8
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MOV_rxi 00100 ... ........ @arith_1i %s
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CMP_xri 00101 ... ........ @arith_1i s=1
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ADD_rri 00110 ... ........ @arith_1i %s
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SUB_rri 00111 ... ........ @arith_1i %s
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# Add, compare, move (two high registers)
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%reg_0_7 7:1 0:3
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@addsub_2h .... .... . rm:4 ... \
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&s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
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ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
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CMP_xrri 0100 0101 . .... ... @addsub_2h s=1
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MOV_rxri 0100 0110 . .... ... @addsub_2h s=0
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# Adjust SP (immediate)
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%imm7_0x4 0:7 !function=times_4
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@addsub_sp_i .... .... . ....... \
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&s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
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ADD_rri 1011 0000 0 ....... @addsub_sp_i
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SUB_rri 1011 0000 1 ....... @addsub_sp_i
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# Branch and exchange
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@branchr .... .... . rm:4 ... &r
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BX 0100 0111 0 .... 000 @branchr
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BLX_r 0100 0111 1 .... 000 @branchr
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BXNS 0100 0111 0 .... 100 @branchr
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BLXNS 0100 0111 1 .... 100 @branchr
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# Extend
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@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0
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SXTAH 1011 0010 00 ... ... @extend
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SXTAB 1011 0010 01 ... ... @extend
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UXTAH 1011 0010 10 ... ... @extend
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UXTAB 1011 0010 11 ... ... @extend
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# Change processor state
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%imod 4:1 !function=plus_2
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SETEND 1011 0110 010 1 E:1 000 &setend
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{
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CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
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CPS_v7m 1011 0110 011 im:1 00 I:1 F:1
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}
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# Reverse bytes
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@rdm .... .... .. rm:3 rd:3 &rr
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REV 1011 1010 00 ... ... @rdm
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REV16 1011 1010 01 ... ... @rdm
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REVSH 1011 1010 11 ... ... @rdm
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# Hints
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{
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{
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YIELD 1011 1111 0001 0000
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WFE 1011 1111 0010 0000
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WFI 1011 1111 0011 0000
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# TODO: Implement SEV, SEVL; may help SMP performance.
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# SEV 1011 1111 0100 0000
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# SEVL 1011 1111 0101 0000
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# The canonical nop has the second nibble as 0000, but the whole of the
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# rest of the space is a reserved hint, behaves as nop.
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NOP 1011 1111 ---- 0000
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}
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IT 1011 1111 cond_mask:8
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}
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# Miscellaneous 16-bit instructions
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%imm6_9_3 9:1 3:5 !function=times_2
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HLT 1011 1010 10 imm:6 &i
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BKPT 1011 1110 imm:8 &i
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CBZ 1011 nz:1 0.1 ..... rn:3 imm=%imm6_9_3
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# Push and Pop
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%push_list 0:9 !function=t16_push_list
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%pop_list 0:9 !function=t16_pop_list
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STM 1011 010 ......... \
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&ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
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LDM_t16 1011 110 ......... \
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&ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
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# Conditional branches, Supervisor call
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%imm8_0x2 0:s8 !function=times_2
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{
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UDF 1101 1110 ---- ----
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SVC 1101 1111 imm:8 &i
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B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2
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}
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# Unconditional Branch
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%imm11_0x2 0:s11 !function=times_2
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B 11100 ........... &i imm=%imm11_0x2
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# thumb_insn_is_16bit() ensures we won't be decoding these as
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# T16 instructions for a Thumb2 CPU, so these patterns must be
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# a Thumb1 split BL/BLX.
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BLX_suffix 11101 imm:11 &i
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BL_BLX_prefix 11110 imm:s11 &i
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BL_suffix 11111 imm:11 &i
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