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9b2d08a066
SR tests generate instructions that the assembler does not recognize and thus must take care about configuration endianness. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
237 lines
3.9 KiB
ArmAsm
237 lines
3.9 KiB
ArmAsm
#include "macros.inc"
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test_suite sr
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#if XCHAL_HAVE_BE
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#define LOW__SR 0x04
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#define HI_RSR 0x30
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#define HI_WSR 0x31
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#define HI_XSR 0x16
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#else
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#define LOW__SR 0x40
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#define HI_RSR 0x03
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#define HI_WSR 0x13
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#define HI_XSR 0x61
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#endif
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.macro sr_op sym, op_sym, op_byte, sr
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.if \sym
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\op_sym a4, \sr
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.else
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.byte LOW__SR, \sr, \op_byte
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.endif
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.endm
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.macro test_sr_op sym, mask, op, op_byte, sr
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movi a4, 0
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.if (\mask)
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set_vector kernel, 0
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sr_op \sym, \op, \op_byte, \sr
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.else
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set_vector kernel, 2f
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1:
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sr_op \sym, \op, \op_byte, \sr
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test_fail
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2:
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reset_ps
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rsr a2, exccause
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assert eqi, a2, 0
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rsr a2, epc1
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movi a3, 1b
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assert eq, a2, a3
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.endif
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.endm
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.macro test_sr_mask sr, sym, mask
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test \sr
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test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr
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test_sr_op \sym, \mask & 2, wsr, HI_WSR, \sr
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test_sr_op \sym, \mask & 4, xsr, HI_XSR, \sr
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test_end
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.endm
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.macro test_sr sr, conf
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test_sr_mask \sr, \conf, 7
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.endm
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#if XCHAL_HAVE_MAC16
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test_sr acchi, 1
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test_sr acclo, 1
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#else
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test_sr_mask /*acchi*/17, 0, 0
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test_sr_mask /*acclo*/16, 0, 0
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#endif
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#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000
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test_sr atomctl, 1
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#else
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test_sr_mask /*atomctl*/99, 0, 0
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#endif
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#if XCHAL_HAVE_BOOLEANS
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test_sr br, 1
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#else
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test_sr_mask /*br*/4, 0, 0
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#endif
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test_sr_mask /*cacheattr*/98, 0, 0
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#if XCHAL_HAVE_CCOUNT
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test_sr ccompare0, 1
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test_sr ccount, 1
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#else
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test_sr_mask /*ccompare0*/240, 0, 0
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test_sr_mask /*ccount*/234, 0, 0
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#endif
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#if XCHAL_HAVE_CP
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test_sr cpenable, 1
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#else
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test_sr_mask /*cpenable*/224, 0, 0
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#endif
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#if XCHAL_HAVE_DEBUG
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#if XCHAL_NUM_DBREAK
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test_sr dbreaka0, 1
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test_sr dbreakc0, 1
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#endif
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test_sr_mask debugcause, 1, 1
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#else
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test_sr_mask /*dbreaka0*/144, 0, 0
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test_sr_mask /*dbreakc0*/160, 0, 0
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test_sr_mask /*debugcause*/233, 0, 0
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#endif
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test_sr depc, 1
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#if XCHAL_HAVE_PTP_MMU
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test_sr dtlbcfg, 1
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#else
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test_sr_mask /*dtlbcfg*/92, 0, 0
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#endif
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test_sr epc1, 1
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#if XCHAL_NUM_INTLEVELS > 1
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test_sr epc2, 1
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test_sr eps2, 1
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#else
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test_sr_mask /*epc2*/178, 0, 0
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test_sr_mask /*eps2*/194, 0, 0
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#endif
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test_sr exccause, 1
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test_sr excsave1, 1
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#if XCHAL_NUM_INTLEVELS > 1
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test_sr excsave2, 1
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#else
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test_sr_mask /*excsave2*/210, 0, 0
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#endif
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test_sr excvaddr, 1
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#if XCHAL_HAVE_DEBUG
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#if XCHAL_NUM_IBREAK
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test_sr ibreaka0, 1
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test_sr ibreakenable, 1
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#endif
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test_sr icount, 1
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test_sr icountlevel, 1
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#else
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test_sr_mask /*ibreaka0*/128, 0, 0
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test_sr_mask /*ibreakenable*/96, 0, 0
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test_sr_mask /*icount*/236, 0, 0
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test_sr_mask /*icountlevel*/237, 0, 0
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#endif
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test_sr_mask /*intclear*/227, 0, 2
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test_sr_mask /*interrupt*/226, 0, 3
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test_sr intenable, 1
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#if XCHAL_HAVE_PTP_MMU
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test_sr itlbcfg, 1
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#else
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test_sr_mask /*itlbcfg*/91, 0, 0
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#endif
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#if XCHAL_HAVE_LOOPS
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test_sr lbeg, 1
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test_sr lcount, 1
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test_sr lend, 1
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#else
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test_sr_mask /*lbeg*/0, 0, 0
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test_sr_mask /*lcount*/2, 0, 0
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test_sr_mask /*lend*/1, 0, 0
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#endif
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#if XCHAL_HAVE_ABSOLUTE_LITERALS
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test_sr litbase, 1
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#else
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test_sr_mask /*litbase*/5, 0, 0
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#endif
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#if XCHAL_HAVE_MAC16
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test_sr m0, 1
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#else
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test_sr_mask /*m0*/32, 0, 0
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#endif
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#if XCHAL_HW_VERSION >= 250000
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test_sr_mask /*memctl*/97, 0, 7
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#else
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test_sr_mask /*memctl*/97, 0, 0
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#endif
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#if XCHAL_NUM_MISC_REGS
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test_sr misc0, 1
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#else
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test_sr_mask /*misc0*/244, 0, 0
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#endif
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#if XCHAL_HAVE_PREFETCH
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test_sr prefctl, 1
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#else
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test_sr_mask /*prefctl*/40, 0, 0
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#endif
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#if XCHAL_HAVE_PRID
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test_sr_mask /*prid*/235, 0, 1
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#else
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test_sr_mask /*prid*/235, 0, 0
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#endif
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test_sr ps, 1
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#if XCHAL_HAVE_PTP_MMU
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test_sr ptevaddr, 1
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test_sr rasid, 1
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#else
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test_sr_mask /*ptevaddr*/83, 0, 0
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test_sr_mask /*rasid*/90, 0, 0
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#endif
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test_sr sar, 1
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#if XCHAL_HAVE_S32C1I
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test_sr scompare1, 1
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#else
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test_sr_mask /*scompare1*/12, 0, 0
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#endif
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#if XCHAL_HAVE_VECBASE
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test_sr vecbase, 1
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#else
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test_sr_mask /*vecbase*/231, 0, 0
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#endif
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#if XCHAL_HAVE_WINDOWED
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test_sr windowbase, 1
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test_sr windowstart, 1
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#else
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test_sr_mask /*windowbase*/72, 0, 0
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test_sr_mask /*windowstart*/73, 0, 0
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#endif
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test_suite_end
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