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583e6a5f55
Xtensa cores may or may not have hardware support for unaligned memory access. Remove TARGET_ALIGNED_ONLY=y from all xtensa configurations and pass MO_ALIGN in memory access flags for all operations that would raise an exception. Simplify use of gen_load_store_alignment by passing access size and alignment requirements in single parameter. Drop condition from xtensa_cpu_do_unaligned_access and replace it with assertion. Add a test. Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
222 lines
4.3 KiB
ArmAsm
222 lines
4.3 KiB
ArmAsm
#include "macros.inc"
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test_suite load_store
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.macro load_ok_test op, type, data, value
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.data
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.align 4
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1:
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\type \data
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.previous
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reset_ps
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set_vector kernel, 0
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movi a3, 1b
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addi a4, a4, 1
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mov a5, a4
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\op a5, a3, 0
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movi a6, \value
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assert eq, a5, a6
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.endm
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION
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.macro load_unaligned_test will_trap, op, type, data, value
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.data
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.align 4
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.byte 0
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1:
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\type \data
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.previous
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reset_ps
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.ifeq \will_trap
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set_vector kernel, 0
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.else
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set_vector kernel, 2f
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.endif
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movi a3, 1b
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addi a4, a4, 1
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mov a5, a4
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1:
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\op a5, a3, 0
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.ifeq \will_trap
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movi a6, \value
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assert eq, a5, a6
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.else
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test_fail
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2:
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rsr a6, exccause
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movi a7, 9
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assert eq, a6, a7
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rsr a6, epc1
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movi a7, 1b
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assert eq, a6, a7
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rsr a6, excvaddr
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assert eq, a6, a3
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assert eq, a5, a4
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.endif
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reset_ps
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.endm
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#else
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.macro load_unaligned_test will_trap, op, type, data, value
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.data
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.align 4
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1:
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\type \data
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.previous
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reset_ps
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set_vector kernel, 0
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movi a3, 1b + 1
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addi a4, a4, 1
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mov a5, a4
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\op a5, a3, 0
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movi a6, \value
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assert eq, a5, a6
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.endm
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#endif
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.macro store_ok_test op, type, value
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.data
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.align 4
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.byte 0, 0, 0, 0x55
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1:
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\type 0
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2:
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.byte 0xaa
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.previous
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reset_ps
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set_vector kernel, 0
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movi a3, 1b
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movi a5, \value
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\op a5, a3, 0
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movi a3, 2b
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l8ui a5, a3, 0
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movi a6, 0xaa
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assert eq, a5, a6
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movi a3, 1b - 1
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l8ui a5, a3, 0
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movi a6, 0x55
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assert eq, a5, a6
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.endm
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#if XCHAL_UNALIGNED_STORE_EXCEPTION
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.macro store_unaligned_test will_trap, op, nop, type, value
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.data
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.align 4
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.byte 0x55
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1:
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\type 0
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2:
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.byte 0xaa
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.previous
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reset_ps
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.ifeq \will_trap
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set_vector kernel, 0
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.else
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set_vector kernel, 4f
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.endif
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movi a3, 1b
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movi a5, \value
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3:
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\op a5, a3, 0
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.ifne \will_trap
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test_fail
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4:
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rsr a6, exccause
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movi a7, 9
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assert eq, a6, a7
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rsr a6, epc1
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movi a7, 3b
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assert eq, a6, a7
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rsr a6, excvaddr
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assert eq, a6, a3
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l8ui a5, a3, 0
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assert eqi, a5, 0
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.endif
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reset_ps
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movi a3, 2b
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l8ui a5, a3, 0
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movi a6, 0xaa
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assert eq, a5, a6
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movi a3, 1b - 1
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l8ui a5, a3, 0
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movi a6, 0x55
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assert eq, a5, a6
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.endm
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#else
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.macro store_unaligned_test will_trap, sop, lop, type, value
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.data
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.align 4
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.byte 0x55
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1:
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\type 0
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.previous
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reset_ps
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set_vector kernel, 0
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movi a3, 1b
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movi a5, \value
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\sop a5, a3, 0
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movi a3, 1b - 1
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\lop a6, a3, 0
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assert eq, a5, a6
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.endm
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#endif
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test load_ok
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load_ok_test l16si, .short, 0x00001234, 0x00001234
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load_ok_test l16si, .short, 0x000089ab, 0xffff89ab
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load_ok_test l16ui, .short, 0x00001234, 0x00001234
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load_ok_test l16ui, .short, 0x000089ab, 0x000089ab
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load_ok_test l32i, .word, 0x12345678, 0x12345678
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#if XCHAL_HAVE_RELEASE_SYNC
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load_ok_test l32ai, .word, 0x12345678, 0x12345678
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#endif
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test_end
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#undef WILL_TRAP
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#if XCHAL_UNALIGNED_LOAD_HW
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#define WILL_TRAP 0
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#else
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#define WILL_TRAP 1
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#endif
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test load_unaligned
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load_unaligned_test WILL_TRAP, l16si, .short, 0x00001234, 0x00001234
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load_unaligned_test WILL_TRAP, l16si, .short, 0x000089ab, 0xffff89ab
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load_unaligned_test WILL_TRAP, l16ui, .short, 0x00001234, 0x00001234
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load_unaligned_test WILL_TRAP, l16ui, .short, 0x000089ab, 0x000089ab
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load_unaligned_test WILL_TRAP, l32i, .word, 0x12345678, 0x12345678
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#if XCHAL_HAVE_RELEASE_SYNC
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load_unaligned_test 1, l32ai, .word, 0x12345678, 0x12345678
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#endif
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test_end
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test store_ok
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store_ok_test s16i, .short, 0x00001234
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store_ok_test s32i, .word, 0x12345678
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#if XCHAL_HAVE_RELEASE_SYNC
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store_ok_test s32ri, .word, 0x12345678
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#endif
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test_end
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#undef WILL_TRAP
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#if XCHAL_UNALIGNED_STORE_HW
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#define WILL_TRAP 0
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#else
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#define WILL_TRAP 1
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#endif
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test store_unaligned
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store_unaligned_test WILL_TRAP, s16i, l16ui, .short, 0x00001234
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store_unaligned_test WILL_TRAP, s32i, l32i, .word, 0x12345678
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#if XCHAL_HAVE_RELEASE_SYNC
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store_unaligned_test 1, s32ri, l32i, .word, 0x12345678
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#endif
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test_end
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test_suite_end
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