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	 11029e949f
			
		
	
	
		11029e949f
		
	
	
	
	
		
			
			Test exact division/sqrt DFPU sequences. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
		
			
				
	
	
		
			83 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			83 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
| #include "macros.inc"
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| #include "fpu.h"
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| 
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| test_suite fp0_div
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| 
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| #if XCHAL_HAVE_FP_DIV
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| 
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| .macro  divs_seq q, a, b, r, y, y0, an, bn, e, ex
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|     div0.s      \y0, \b
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|     nexp01.s    \bn, \b
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|     const.s     \e, 1
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|     maddn.s     \e, \bn, \y0
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|     mov.s       \y, \y0
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|     mov.s       \ex, \b
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|     nexp01.s    \an, \a
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|     maddn.s     \y, \e, \y0
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|     const.s     \e, 1
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|     const.s     \q, 0
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|     neg.s       \r, \an
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|     maddn.s     \e, \bn, \y
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|     maddn.s     \q, \r, \y0
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|     mkdadj.s    \ex, \a
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|     maddn.s     \y, \e, \y
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|     maddn.s     \r, \bn, \q
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|     const.s     \e, 1
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|     maddn.s     \e, \bn, \y
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|     maddn.s     \q, \r, \y
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|     neg.s       \r, \an
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|     maddn.s     \y, \e, \y
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|     maddn.s     \r, \bn, \q
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|     addexpm.s   \q, \ex
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|     addexp.s    \y, \ex
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|     divn.s      \q, \r, \y
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| .endm
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| 
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| .macro div_s fr0, fr1, fr2
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|     divs_seq    \fr0, \fr1, \fr2, f9, f10, f11, f12, f13, f14, f15
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| .endm
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| 
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| .macro movfp fr, v
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|     movi        a2, \v
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|     wfr         \fr, a2
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| .endm
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| 
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| .macro check_res fr, r, sr
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|     rfr         a2, \fr
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|     dump        a2
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|     movi        a3, \r
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|     assert      eq, a2, a3
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|     rur         a2, fsr
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|     movi        a3, \sr
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|     assert      eq, a2, a3
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| .endm
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| 
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| test div_s
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|     movi        a2, 1
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|     wsr         a2, cpenable
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| 
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|     test_op2    div_s, f0, f1, f2, 0x40000000, 0x40400000, \
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|         0x3f2aaaab, 0x3f2aaaaa, 0x3f2aaaab, 0x3f2aaaaa, \
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|              FSR_I,      FSR_I,      FSR_I,      FSR_I
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|     test_op2    div_s, f3, f4, f5, F32_1, F32_0, \
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|         F32_PINF, F32_PINF, F32_PINF, F32_PINF, \
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|            FSR_Z,    FSR_Z,    FSR_Z,    FSR_Z
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|     test_op2    div_s, f6, f7, f8, F32_0, F32_0, \
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|         F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
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|            FSR_V,    FSR_V,    FSR_V,    FSR_V
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| 
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|     /* MAX_FLOAT / 0.5 = +inf/MAX_FLOAT  */
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|     test_op2    div_s, f0, f1, f2, F32_MAX, F32_0_5, \
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|         F32_PINF, F32_MAX, F32_PINF, F32_MAX, \
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|           FSR_OI,  FSR_OI,   FSR_OI,  FSR_OI
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| 
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|     /* 0.5 / MAX_FLOAT = denorm  */
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|     test_op2    div_s, f0, f1, f2, F32_0_5, F32_MAX, \
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|         0x00100000, 0x00100000, 0x00100001, 0x00100000, \
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|             FSR_UI,     FSR_UI,     FSR_UI,     FSR_UI
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| test_end
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| 
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| #endif
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| 
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| test_suite_end
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