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905bdf72a6
To avoid callers to emit dead code if check_cp0_enabled() raise an exception, let it return a boolean value, whether CP0 is enabled or not. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210420193453.1913810-4-f4bug@amsat.org>
201 lines
6.4 KiB
C
201 lines
6.4 KiB
C
/*
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* MIPS translation routines.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef TARGET_MIPS_TRANSLATE_H
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#define TARGET_MIPS_TRANSLATE_H
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#include "exec/translator.h"
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#define MIPS_DEBUG_DISAS 0
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typedef struct DisasContext {
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DisasContextBase base;
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target_ulong saved_pc;
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target_ulong page_start;
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uint32_t opcode;
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uint64_t insn_flags;
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int32_t CP0_Config1;
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int32_t CP0_Config2;
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int32_t CP0_Config3;
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int32_t CP0_Config5;
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/* Routine used to access memory */
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int mem_idx;
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MemOp default_tcg_memop_mask;
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uint32_t hflags, saved_hflags;
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target_ulong btarget;
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bool ulri;
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int kscrexist;
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bool rxi;
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int ie;
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bool bi;
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bool bp;
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uint64_t PAMask;
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bool mvh;
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bool eva;
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bool sc;
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int CP0_LLAddr_shift;
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bool ps;
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bool vp;
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bool cmgcr;
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bool mrp;
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bool nan2008;
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bool abs2008;
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bool saar;
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bool mi;
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int gi;
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} DisasContext;
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/* MIPS major opcodes */
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#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
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#define OPC_CP1 (0x11 << 26)
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/* Coprocessor 1 (rs field) */
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#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
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/* Values for the fmt field in FP instructions */
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enum {
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/* 0 - 15 are reserved */
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FMT_S = 16, /* single fp */
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FMT_D = 17, /* double fp */
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FMT_E = 18, /* extended fp */
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FMT_Q = 19, /* quad fp */
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FMT_W = 20, /* 32-bit fixed */
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FMT_L = 21, /* 64-bit fixed */
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FMT_PS = 22, /* paired single fp */
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/* 23 - 31 are reserved */
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};
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enum {
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OPC_MFC1 = (0x00 << 21) | OPC_CP1,
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OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
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OPC_CFC1 = (0x02 << 21) | OPC_CP1,
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OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
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OPC_MTC1 = (0x04 << 21) | OPC_CP1,
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OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
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OPC_CTC1 = (0x06 << 21) | OPC_CP1,
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OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
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OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
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OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
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OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
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OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
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OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
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OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
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OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1,
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OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
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OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
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OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
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OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
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OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
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};
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#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
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#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
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enum {
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OPC_BC1F = (0x00 << 16) | OPC_BC1,
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OPC_BC1T = (0x01 << 16) | OPC_BC1,
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OPC_BC1FL = (0x02 << 16) | OPC_BC1,
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OPC_BC1TL = (0x03 << 16) | OPC_BC1,
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};
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enum {
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OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
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OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
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};
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enum {
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OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
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OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
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};
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void generate_exception(DisasContext *ctx, int excp);
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void generate_exception_err(DisasContext *ctx, int excp, int err);
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void generate_exception_end(DisasContext *ctx, int excp);
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void gen_reserved_instruction(DisasContext *ctx);
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void check_insn(DisasContext *ctx, uint64_t flags);
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void check_mips_64(DisasContext *ctx);
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/**
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* check_cp0_enabled:
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* Return %true if CP0 is enabled, otherwise return %false
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* and emit a 'coprocessor unusable' exception.
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*/
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bool check_cp0_enabled(DisasContext *ctx);
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void check_cp1_enabled(DisasContext *ctx);
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void check_cp1_64bitmode(DisasContext *ctx);
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void check_cp1_registers(DisasContext *ctx, int regs);
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void check_cop1x(DisasContext *ctx);
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void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
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void gen_move_low32(TCGv ret, TCGv_i64 arg);
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void gen_move_high32(TCGv ret, TCGv_i64 arg);
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void gen_load_gpr(TCGv t, int reg);
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void gen_store_gpr(TCGv t, int reg);
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#if defined(TARGET_MIPS64)
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void gen_load_gpr_hi(TCGv_i64 t, int reg);
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void gen_store_gpr_hi(TCGv_i64 t, int reg);
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#endif /* TARGET_MIPS64 */
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void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
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void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
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void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
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void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
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int get_fp_bit(int cc);
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/*
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* Address Computation and Large Constant Instructions
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*/
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void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
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bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
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bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
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void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
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extern TCGv cpu_gpr[32], cpu_PC;
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#if defined(TARGET_MIPS64)
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extern TCGv_i64 cpu_gpr_hi[32];
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#endif
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extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
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extern TCGv_i32 fpu_fcr0, fpu_fcr31;
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extern TCGv_i64 fpu_f64[32];
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extern TCGv bcond;
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#define LOG_DISAS(...) \
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do { \
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if (MIPS_DEBUG_DISAS) { \
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qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
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} \
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} while (0)
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#define MIPS_INVAL(op) \
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do { \
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if (MIPS_DEBUG_DISAS) { \
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qemu_log_mask(CPU_LOG_TB_IN_ASM, \
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TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
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ctx->base.pc_next, ctx->opcode, op, \
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ctx->opcode >> 26, ctx->opcode & 0x3F, \
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((ctx->opcode >> 16) & 0x1F)); \
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} \
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} while (0)
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/* MSA */
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void msa_translate_init(void);
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/* MXU */
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void mxu_translate_init(void);
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bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
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/* decodetree generated */
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bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
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bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
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bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
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#if defined(TARGET_MIPS64)
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bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
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#endif
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#endif
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