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8df9f0c3d7
With the exception of hw/core/, the hw/ directory only contains device models used in system emulation. Semihosting is also used by user emulation. As a generic feature, move it out of hw/ directory. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210226131356.3964782-3-f4bug@amsat.org> Message-Id: <20210305135451.15427-3-alex.bennee@linaro.org>
40 lines
1.5 KiB
C
40 lines
1.5 KiB
C
/*
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* Semihosting support for systems modeled on the Arm "Angel"
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* semihosting syscalls design. This includes Arm and RISC-V processors
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*
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* Copyright (c) 2005, 2007 CodeSourcery.
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* Copyright (c) 2019 Linaro
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* Written by Paul Brook.
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*
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* Copyright © 2020 by Keith Packard <keithp@keithp.com>
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* Adapted for systems other than ARM, including RISC-V, by Keith Packard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* ARM Semihosting is documented in:
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* Semihosting for AArch32 and AArch64 Release 2.0
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* https://static.docs.arm.com/100863/0200/semihosting.pdf
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*
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* RISC-V Semihosting is documented in:
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* RISC-V Semihosting
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* https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
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*/
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#ifndef COMMON_SEMI_H
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#define COMMON_SEMI_H
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target_ulong do_common_semihosting(CPUState *cs);
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#endif /* COMMON_SEMI_H */
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