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8063396bf3
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
81 lines
2.8 KiB
C
81 lines
2.8 KiB
C
/*
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* ARM TrustZone master security controller emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the TrustZone master security controller (MSC).
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* It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
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* (DDI 0571G):
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* https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
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*
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* The MSC sits in front of a device which can be a bus master (such as
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* a DMA controller) and allows secure software to configure it to either
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* pass through or reject transactions made by that bus master.
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* Rejected transactions may be configured to either be aborted, or to
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* behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
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*
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* The MSC has no register interface -- it is configured purely by a
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* collection of input signals from other hardware in the system. Typically
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* they are either hardwired or exposed in an ad-hoc register interface by
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* the SoC that uses the MSC.
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*
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* We don't currently implement the irq_enable GPIO input, because on
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* the MPS2 FPGA images it is always tied high, which is awkward to
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* implement in QEMU.
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*
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* QEMU interface:
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* + Named GPIO input "cfg_nonsec": set to 1 if the bus master should be
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* treated as nonsecure, or 0 for secure
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* + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should
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* result in a transaction error, or 0 for the transaction to RAZ/WI
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* + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
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* + Named GPIO output "irq": set for a transaction-failed interrupt
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* + Property "downstream": MemoryRegion defining where bus master transactions
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* are made if they are not blocked
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* + Property "idau": an object implementing IDAUInterface, which defines which
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* addresses should be treated as secure and which as non-secure.
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* This need not be the same IDAU as the one used by the CPU.
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* + sysbus MMIO region 0: MemoryRegion defining the upstream end of the MSC;
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* this should be passed to the bus master device as the region it should
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* make memory transactions to
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*/
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#ifndef TZ_MSC_H
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#define TZ_MSC_H
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#include "hw/sysbus.h"
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#include "target/arm/idau.h"
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#include "qom/object.h"
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#define TYPE_TZ_MSC "tz-msc"
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OBJECT_DECLARE_SIMPLE_TYPE(TZMSC, TZ_MSC)
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struct TZMSC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/* State: these just track the values of our input signals */
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bool cfg_nonsec;
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bool cfg_sec_resp;
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bool irq_clear;
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/* State: are we asserting irq ? */
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bool irq_status;
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qemu_irq irq;
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MemoryRegion *downstream;
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AddressSpace downstream_as;
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MemoryRegion upstream;
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IDAUInterface *idau;
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};
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#endif
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