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f4b2add6cc
Most clocks supported by the CCM are useless to the qemu framework. Only clocks related to timers (EPIT, GPT, PWM, WATCHDOG, ...) are usefull to QEMU code. Therefore this patch removes clock computation handling for all clocks but: * CLK_NONE, * CLK_IPG, * CLK_32k Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 9e7222efb349801032e60c0f6b0fbad0e5dcf648.1456868959.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
317 lines
8.2 KiB
C
317 lines
8.2 KiB
C
/*
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* IMX25 Clock Control Module
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*
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* Copyright (C) 2012 NICTA
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* To get the timer frequencies right, we need to emulate at least part of
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* the CCM.
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*/
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#include "qemu/osdep.h"
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#include "hw/misc/imx25_ccm.h"
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#ifndef DEBUG_IMX25_CCM
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#define DEBUG_IMX25_CCM 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX25_CCM) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX25_CCM, \
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__func__, ##args); \
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} \
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} while (0)
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static char const *imx25_ccm_reg_name(uint32_t reg)
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{
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static char unknown[20];
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switch (reg) {
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case IMX25_CCM_MPCTL_REG:
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return "mpctl";
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case IMX25_CCM_UPCTL_REG:
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return "upctl";
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case IMX25_CCM_CCTL_REG:
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return "cctl";
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case IMX25_CCM_CGCR0_REG:
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return "cgcr0";
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case IMX25_CCM_CGCR1_REG:
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return "cgcr1";
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case IMX25_CCM_CGCR2_REG:
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return "cgcr2";
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case IMX25_CCM_PCDR0_REG:
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return "pcdr0";
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case IMX25_CCM_PCDR1_REG:
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return "pcdr1";
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case IMX25_CCM_PCDR2_REG:
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return "pcdr2";
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case IMX25_CCM_PCDR3_REG:
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return "pcdr3";
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case IMX25_CCM_RCSR_REG:
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return "rcsr";
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case IMX25_CCM_CRDR_REG:
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return "crdr";
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case IMX25_CCM_DCVR0_REG:
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return "dcvr0";
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case IMX25_CCM_DCVR1_REG:
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return "dcvr1";
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case IMX25_CCM_DCVR2_REG:
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return "dcvr2";
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case IMX25_CCM_DCVR3_REG:
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return "dcvr3";
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case IMX25_CCM_LTR0_REG:
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return "ltr0";
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case IMX25_CCM_LTR1_REG:
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return "ltr1";
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case IMX25_CCM_LTR2_REG:
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return "ltr2";
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case IMX25_CCM_LTR3_REG:
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return "ltr3";
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case IMX25_CCM_LTBR0_REG:
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return "ltbr0";
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case IMX25_CCM_LTBR1_REG:
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return "ltbr1";
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case IMX25_CCM_PMCR0_REG:
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return "pmcr0";
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case IMX25_CCM_PMCR1_REG:
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return "pmcr1";
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case IMX25_CCM_PMCR2_REG:
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return "pmcr2";
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case IMX25_CCM_MCR_REG:
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return "mcr";
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case IMX25_CCM_LPIMR0_REG:
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return "lpimr0";
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case IMX25_CCM_LPIMR1_REG:
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return "lpimr1";
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default:
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sprintf(unknown, "[%d ?]", reg);
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return unknown;
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}
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}
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#define CKIH_FREQ 24000000 /* 24MHz crystal input */
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static const VMStateDescription vmstate_imx25_ccm = {
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.name = TYPE_IMX25_CCM,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(reg, IMX25CCMState, IMX25_CCM_MAX_REG),
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VMSTATE_END_OF_LIST()
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},
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};
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static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev)
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{
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uint32_t freq;
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IMX25CCMState *s = IMX25_CCM(dev);
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if (EXTRACT(s->reg[IMX25_CCM_CCTL_REG], MPLL_BYPASS)) {
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freq = CKIH_FREQ;
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} else {
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freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ);
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}
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DPRINTF("freq = %d\n", freq);
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return freq;
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}
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static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev)
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{
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uint32_t freq;
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IMX25CCMState *s = IMX25_CCM(dev);
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freq = imx25_ccm_get_mpll_clk(dev);
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if (EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_SRC)) {
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freq = (freq * 3 / 4);
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}
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freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV));
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DPRINTF("freq = %d\n", freq);
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return freq;
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}
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static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev)
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{
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uint32_t freq;
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IMX25CCMState *s = IMX25_CCM(dev);
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freq = imx25_ccm_get_mcu_clk(dev)
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/ (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV));
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DPRINTF("freq = %d\n", freq);
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return freq;
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}
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static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev)
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{
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uint32_t freq;
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freq = imx25_ccm_get_ahb_clk(dev) / 2;
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DPRINTF("freq = %d\n", freq);
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return freq;
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}
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static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
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{
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uint32_t freq = 0;
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DPRINTF("Clock = %d)\n", clock);
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switch (clock) {
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case CLK_NONE:
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break;
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case CLK_IPG:
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freq = imx25_ccm_get_ipg_clk(dev);
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break;
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case CLK_32k:
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freq = CKIL_FREQ;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
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TYPE_IMX25_CCM, __func__, clock);
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break;
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}
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DPRINTF("Clock = %d) = %d\n", clock, freq);
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return freq;
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}
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static void imx25_ccm_reset(DeviceState *dev)
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{
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IMX25CCMState *s = IMX25_CCM(dev);
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DPRINTF("\n");
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memset(s->reg, 0, IMX25_CCM_MAX_REG * sizeof(uint32_t));
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s->reg[IMX25_CCM_MPCTL_REG] = 0x800b2c01;
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s->reg[IMX25_CCM_UPCTL_REG] = 0x84042800;
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/*
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* The value below gives:
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* CPU = 133 MHz, AHB = 66,5 MHz, IPG = 33 MHz.
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*/
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s->reg[IMX25_CCM_CCTL_REG] = 0xd0030000;
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s->reg[IMX25_CCM_CGCR0_REG] = 0x028A0100;
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s->reg[IMX25_CCM_CGCR1_REG] = 0x04008100;
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s->reg[IMX25_CCM_CGCR2_REG] = 0x00000438;
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s->reg[IMX25_CCM_PCDR0_REG] = 0x01010101;
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s->reg[IMX25_CCM_PCDR1_REG] = 0x01010101;
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s->reg[IMX25_CCM_PCDR2_REG] = 0x01010101;
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s->reg[IMX25_CCM_PCDR3_REG] = 0x01010101;
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s->reg[IMX25_CCM_PMCR0_REG] = 0x00A00000;
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s->reg[IMX25_CCM_PMCR1_REG] = 0x0000A030;
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s->reg[IMX25_CCM_PMCR2_REG] = 0x0000A030;
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s->reg[IMX25_CCM_MCR_REG] = 0x43000000;
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/*
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* default boot will change the reset values to allow:
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* CPU = 399 MHz, AHB = 133 MHz, IPG = 66,5 MHz.
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* For some reason, this doesn't work. With the value below, linux
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* detects a 88 MHz IPG CLK instead of 66,5 MHz.
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s->reg[IMX25_CCM_CCTL_REG] = 0x20032000;
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*/
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}
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static uint64_t imx25_ccm_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t value = 0;
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IMX25CCMState *s = (IMX25CCMState *)opaque;
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if (offset < 0x70) {
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value = s->reg[offset >> 2];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX25_CCM, __func__, offset);
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}
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DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx25_ccm_reg_name(offset >> 2),
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value);
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return value;
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}
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static void imx25_ccm_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMX25CCMState *s = (IMX25CCMState *)opaque;
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DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx25_ccm_reg_name(offset >> 2),
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(uint32_t)value);
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if (offset < 0x70) {
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/*
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* We will do a better implementation later. In particular some bits
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* cannot be written to.
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*/
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s->reg[offset >> 2] = value;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX25_CCM, __func__, offset);
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}
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}
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static const struct MemoryRegionOps imx25_ccm_ops = {
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.read = imx25_ccm_read,
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.write = imx25_ccm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the real
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* device but in practice there is no reason for a guest to access
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* this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void imx25_ccm_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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SysBusDevice *sd = SYS_BUS_DEVICE(obj);
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IMX25CCMState *s = IMX25_CCM(obj);
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memory_region_init_io(&s->iomem, OBJECT(dev), &imx25_ccm_ops, s,
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TYPE_IMX25_CCM, 0x1000);
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sysbus_init_mmio(sd, &s->iomem);
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}
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static void imx25_ccm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
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dc->reset = imx25_ccm_reset;
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dc->vmsd = &vmstate_imx25_ccm;
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dc->desc = "i.MX25 Clock Control Module";
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ccm->get_clock_frequency = imx25_ccm_get_clock_frequency;
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}
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static const TypeInfo imx25_ccm_info = {
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.name = TYPE_IMX25_CCM,
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.parent = TYPE_IMX_CCM,
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.instance_size = sizeof(IMX25CCMState),
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.instance_init = imx25_ccm_init,
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.class_init = imx25_ccm_class_init,
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};
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static void imx25_ccm_register_types(void)
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{
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type_register_static(&imx25_ccm_info);
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}
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type_init(imx25_ccm_register_types)
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