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9746e583fe
The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level guest interrupt files. This patch adds device emulation for RISC-V AIA IMSIC which supports M-level, S-level, and VS-level MSIs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220220085526.808674-3-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/*
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* RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_IMSIC_H
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#define HW_RISCV_IMSIC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_RISCV_IMSIC "riscv.imsic"
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typedef struct RISCVIMSICState RISCVIMSICState;
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DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC)
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#define IMSIC_MMIO_PAGE_SHIFT 12
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#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT)
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#define IMSIC_MMIO_SIZE(__num_pages) ((__num_pages) * IMSIC_MMIO_PAGE_SZ)
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#define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6
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#define IMSIC_MMIO_GROUP_MIN_SHIFT 24
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#define IMSIC_HART_NUM_GUESTS(__guest_bits) \
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(1U << (__guest_bits))
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#define IMSIC_HART_SIZE(__guest_bits) \
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(IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ)
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#define IMSIC_GROUP_NUM_HARTS(__hart_bits) \
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(1U << (__hart_bits))
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#define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits) \
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(IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits))
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struct RISCVIMSICState {
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/*< private >*/
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SysBusDevice parent_obj;
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qemu_irq *external_irqs;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t num_eistate;
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uint32_t *eidelivery;
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uint32_t *eithreshold;
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uint32_t *eistate;
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/* config */
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bool mmode;
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uint32_t hartid;
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uint32_t num_pages;
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uint32_t num_irqs;
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};
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DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
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uint32_t num_pages, uint32_t num_ids);
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#endif
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