qemu/target/mips
Alex Richardson ec860426df target/mips: Fix handling of LL/SC instructions after 7dd547e5ab
After 7dd547e5ab the env->llval value
is loaded as an unsigned value (instead of sign-extended as before).
Therefore, the CMPXCHG in gen_st_cond() in translate.c fails if the
sign bit is set in the loaded value.

Fix this by sign-extending the llval value for the 32-bit case.

I discovered this issue because FreeBSD MIPS64 was looping forever
in an atomic helper function when trying to start /sbin/init.

Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Fixes: 7dd547e5ab ("target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX")
Buglink: https://bugs.launchpad.net/qemu/+bug/1861605
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Aleksandar Markovic <amarkovic@wavecomp.com>
Cc: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: James Clarke <jrtc27@jrtc27.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200202153409.28534-1-jrtc27@jrtc27.com>
2020-02-04 08:51:41 +01:00
..
cp0_timer.c target/mips: Style improvements in cp0_timer.c 2019-08-19 19:53:37 +02:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu-qom.h hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ 2019-08-21 13:24:01 +02:00
cpu.c cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
cpu.h target/mips: Add implementation of GINVT instruction 2020-01-29 19:28:52 +01:00
dsp_helper.c target/mips: Clean up dsp_helper.c 2019-06-01 20:20:20 +02:00
gdbstub.c target/mips: gdbstub: Revert commit 8e0b373 2019-09-12 18:25:34 +02:00
helper.c target/mips: Add implementation of GINVT instruction 2020-01-29 19:28:52 +01:00
helper.h target/mips: Add implementation of GINVT instruction 2020-01-29 19:28:52 +01:00
internal.h target/mips: Add implementation of GINVT instruction 2020-01-29 19:28:52 +01:00
kvm_mips.h target/mips: Clean up kvm_mips.h 2019-10-01 16:37:50 +02:00
kvm.c kvm: introduce kvm_kernel_irqchip_* functions 2019-12-17 19:32:45 +01:00
lmi_helper.c target/mips: Clean up lmi_helper.c 2019-06-01 20:20:20 +02:00
machine.c target/mips: Amend CP0 WatchHi register implementation 2020-01-29 19:28:52 +01:00
Makefile.objs target/mips: only build mips-semi for softmmu 2019-05-28 10:28:51 +01:00
mips-defs.h target/mips: Clean up mips-defs.h 2019-10-01 16:41:03 +02:00
mips-semi.c target/mips: semihosting: Remove 'uhi_done' label in helper_do_semihosting() 2020-01-29 19:28:52 +01:00
msa_helper.c target/mips: Refactor handling of vector compare 'less than' (signed) instructions 2019-10-25 18:37:01 +02:00
op_helper.c target/mips: Fix handling of LL/SC instructions after 7dd547e5ab 2020-02-04 08:51:41 +01:00
TODO Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
trace-events trace-events: Shorten file names in comments 2019-03-22 16:18:07 +00:00
translate_init.inc.c target/mips: Use env_cpu, env_archcpu 2019-06-10 07:03:42 -07:00
translate.c target/mips: Add implementation of GINVT instruction 2020-01-29 19:28:52 +01:00