mirror of
https://github.com/qemu/qemu.git
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e688df6bc4
This cleanup makes the number of objects depending on qapi/error.h
drop from 1910 (out of 4743) to 1612 in my "build everything" tree.
While there, separate #include from file comment with a blank line,
and drop a useless comment on why qemu/osdep.h is included first.
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20180201111846.21846-5-armbru@redhat.com>
[Semantic conflict with commit 34e304e975 resolved, OSX breakage fixed]
225 lines
7.3 KiB
C
225 lines
7.3 KiB
C
/*
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* STM32F405 SPI
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/ssi/stm32f2xx_spi.h"
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#ifndef STM_SPI_ERR_DEBUG
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#define STM_SPI_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(lvl, fmt, args...) do { \
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if (STM_SPI_ERR_DEBUG >= lvl) { \
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qemu_log("%s: " fmt, __func__, ## args); \
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} \
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} while (0)
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#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
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static void stm32f2xx_spi_reset(DeviceState *dev)
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{
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STM32F2XXSPIState *s = STM32F2XX_SPI(dev);
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s->spi_cr1 = 0x00000000;
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s->spi_cr2 = 0x00000000;
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s->spi_sr = 0x0000000A;
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s->spi_dr = 0x0000000C;
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s->spi_crcpr = 0x00000007;
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s->spi_rxcrcr = 0x00000000;
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s->spi_txcrcr = 0x00000000;
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s->spi_i2scfgr = 0x00000000;
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s->spi_i2spr = 0x00000002;
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}
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static void stm32f2xx_spi_transfer(STM32F2XXSPIState *s)
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{
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DB_PRINT("Data to send: 0x%x\n", s->spi_dr);
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s->spi_dr = ssi_transfer(s->ssi, s->spi_dr);
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s->spi_sr |= STM_SPI_SR_RXNE;
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DB_PRINT("Data received: 0x%x\n", s->spi_dr);
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}
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static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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STM32F2XXSPIState *s = opaque;
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DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
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switch (addr) {
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case STM_SPI_CR1:
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return s->spi_cr1;
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case STM_SPI_CR2:
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qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n",
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__func__);
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return s->spi_cr2;
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case STM_SPI_SR:
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return s->spi_sr;
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case STM_SPI_DR:
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stm32f2xx_spi_transfer(s);
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s->spi_sr &= ~STM_SPI_SR_RXNE;
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return s->spi_dr;
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case STM_SPI_CRCPR:
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qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
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"are included for compatibility\n", __func__);
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return s->spi_crcpr;
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case STM_SPI_RXCRCR:
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qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
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"are included for compatibility\n", __func__);
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return s->spi_rxcrcr;
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case STM_SPI_TXCRCR:
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qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
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"are included for compatibility\n", __func__);
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return s->spi_txcrcr;
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case STM_SPI_I2SCFGR:
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qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
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"are included for compatibility\n", __func__);
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return s->spi_i2scfgr;
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case STM_SPI_I2SPR:
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qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
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"are included for compatibility\n", __func__);
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return s->spi_i2spr;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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}
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return 0;
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}
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static void stm32f2xx_spi_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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STM32F2XXSPIState *s = opaque;
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uint32_t value = val64;
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DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value);
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switch (addr) {
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case STM_SPI_CR1:
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s->spi_cr1 = value;
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return;
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case STM_SPI_CR2:
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"Interrupts and DMA are not implemented\n", __func__);
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s->spi_cr2 = value;
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return;
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case STM_SPI_SR:
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/* Read only register, except for clearing the CRCERR bit, which
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* is not supported
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*/
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return;
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case STM_SPI_DR:
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s->spi_dr = value;
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stm32f2xx_spi_transfer(s);
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return;
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case STM_SPI_CRCPR:
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qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__);
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return;
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case STM_SPI_RXCRCR:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
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"0x%" HWADDR_PRIx "\n", __func__, addr);
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return;
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case STM_SPI_TXCRCR:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
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"0x%" HWADDR_PRIx "\n", __func__, addr);
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return;
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case STM_SPI_I2SCFGR:
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"I2S is not implemented\n", __func__);
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return;
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case STM_SPI_I2SPR:
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qemu_log_mask(LOG_UNIMP, "%s: " \
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"I2S is not implemented\n", __func__);
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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}
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static const MemoryRegionOps stm32f2xx_spi_ops = {
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.read = stm32f2xx_spi_read,
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.write = stm32f2xx_spi_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_stm32f2xx_spi = {
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.name = TYPE_STM32F2XX_SPI,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(spi_cr1, STM32F2XXSPIState),
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VMSTATE_UINT32(spi_cr2, STM32F2XXSPIState),
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VMSTATE_UINT32(spi_sr, STM32F2XXSPIState),
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VMSTATE_UINT32(spi_dr, STM32F2XXSPIState),
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VMSTATE_UINT32(spi_crcpr, STM32F2XXSPIState),
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VMSTATE_UINT32(spi_rxcrcr, STM32F2XXSPIState),
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VMSTATE_UINT32(spi_txcrcr, STM32F2XXSPIState),
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VMSTATE_UINT32(spi_i2scfgr, STM32F2XXSPIState),
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VMSTATE_UINT32(spi_i2spr, STM32F2XXSPIState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void stm32f2xx_spi_init(Object *obj)
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{
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STM32F2XXSPIState *s = STM32F2XX_SPI(obj);
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DeviceState *dev = DEVICE(obj);
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memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s,
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TYPE_STM32F2XX_SPI, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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s->ssi = ssi_create_bus(dev, "ssi");
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}
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static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = stm32f2xx_spi_reset;
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dc->vmsd = &vmstate_stm32f2xx_spi;
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}
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static const TypeInfo stm32f2xx_spi_info = {
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.name = TYPE_STM32F2XX_SPI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32F2XXSPIState),
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.instance_init = stm32f2xx_spi_init,
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.class_init = stm32f2xx_spi_class_init,
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};
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static void stm32f2xx_spi_register_types(void)
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{
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type_register_static(&stm32f2xx_spi_info);
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}
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type_init(stm32f2xx_spi_register_types)
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