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e9fce79861
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
116 lines
4.3 KiB
Plaintext
116 lines
4.3 KiB
Plaintext
/*
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* Bochs/QEMU ACPI DSDT ASL definition
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Copyright (c) 2010 Isaku Yamahata
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* yamahata at valinux co jp
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* Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
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*/
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ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
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DefinitionBlock (
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"q35-acpi-dsdt.aml",// Output Filename
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"DSDT", // Signature
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0x01, // DSDT Compliance Revision
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"BXPC", // OEMID
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"BXDSDT", // TABLE ID
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0x2 // OEM Revision
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)
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{
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Scope(\_SB) {
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OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
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OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
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Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
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PCIB, 8,
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}
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}
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/****************************************************************
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* PCI Bus definition
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****************************************************************/
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Scope(\_SB) {
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Device(PCI0) {
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Name(_HID, EisaId("PNP0A08"))
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Name(_CID, EisaId("PNP0A03"))
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Name(_ADR, 0x00)
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Name(_UID, 1)
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External(ISA, DeviceObj)
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// _OSC: based on sample of ACPI3.0b spec
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Name(SUPP, 0) // PCI _OSC Support Field value
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Name(CTRL, 0) // PCI _OSC Control Field value
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Method(_OSC, 4) {
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// Create DWORD-addressable fields from the Capabilities Buffer
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CreateDWordField(Arg3, 0, CDW1)
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// Check for proper UUID
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If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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// Create DWORD-addressable fields from the Capabilities Buffer
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CreateDWordField(Arg3, 4, CDW2)
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CreateDWordField(Arg3, 8, CDW3)
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// Save Capabilities DWORD2 & 3
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Store(CDW2, SUPP)
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Store(CDW3, CTRL)
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// Always allow native PME, AER (no dependencies)
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// Never allow SHPC (no SHPC controller in this system)
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And(CTRL, 0x1D, CTRL)
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#if 0 // For now, nothing to do
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If (Not(And(CDW1, 1))) { // Query flag clear?
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// Disable GPEs for features granted native control.
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If (And(CTRL, 0x01)) { // Hot plug control granted?
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Store(0, HPCE) // clear the hot plug SCI enable bit
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Store(1, HPCS) // clear the hot plug SCI status bit
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}
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If (And(CTRL, 0x04)) { // PME control granted?
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Store(0, PMCE) // clear the PME SCI enable bit
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Store(1, PMCS) // clear the PME SCI status bit
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}
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If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
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// Set status to not restore PCI Express cap structure
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// upon resume from S3
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Store(1, S3CR)
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}
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}
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#endif
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If (LNotEqual(Arg1, One)) {
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// Unknown revision
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Or(CDW1, 0x08, CDW1)
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}
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If (LNotEqual(CDW3, CTRL)) {
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// Capabilities bits were masked
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Or(CDW1, 0x10, CDW1)
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}
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// Update DWORD3 in the buffer
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Store(CTRL, CDW3)
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} Else {
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Or(CDW1, 4, CDW1) // Unrecognized UUID
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}
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Return (Arg3)
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}
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}
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}
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}
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