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The Aspeed SOCs have two SD/MMC controllers. Add a device that encapsulates both of these controllers and models the Aspeed-specific registers and behavior. Tested by reading from mmcblk0 in Linux: qemu-system-arm -machine romulus-bmc -nographic \ -drive file=flash-romulus,format=raw,if=mtd \ -device sd-card,drive=sd0 -drive file=_tmp/kernel,format=raw,if=sd,id=sd0 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190925143248.10000-3-clg@kaod.org [clg: - changed the controller MMIO window size to 0x1000 - moved the MMIO mapping of the SDHCI slots at the SoC level - merged code to add SD drives on the SD buses at the machine level ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35 lines
833 B
C
35 lines
833 B
C
/*
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* Aspeed SD Host Controller
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* Eddie James <eajames@linux.ibm.com>
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*
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* Copyright (C) 2019 IBM Corp
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* SPDX-License-Identifer: GPL-2.0-or-later
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*/
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#ifndef ASPEED_SDHCI_H
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#define ASPEED_SDHCI_H
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#include "hw/sd/sdhci.h"
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#define TYPE_ASPEED_SDHCI "aspeed.sdhci"
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#define ASPEED_SDHCI(obj) OBJECT_CHECK(AspeedSDHCIState, (obj), \
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TYPE_ASPEED_SDHCI)
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#define ASPEED_SDHCI_CAPABILITIES 0x01E80080
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#define ASPEED_SDHCI_NUM_SLOTS 2
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#define ASPEED_SDHCI_NUM_REGS (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t))
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#define ASPEED_SDHCI_REG_SIZE 0x100
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typedef struct AspeedSDHCIState {
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SysBusDevice parent;
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SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS];
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t regs[ASPEED_SDHCI_NUM_REGS];
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} AspeedSDHCIState;
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#endif /* ASPEED_SDHCI_H */
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