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ee86213aa3
Stop including exec/address-spaces.h in files that don't need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-5-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
368 lines
9.3 KiB
C
368 lines
9.3 KiB
C
/*
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* HP-PARISC Lasi chipset emulation.
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*
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* (C) 2019 by Helge Deller <deller@gmx.de>
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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* Documentation available at:
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* https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/runstate.h"
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#include "hppa_sys.h"
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#include "hw/net/lasi_82596.h"
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#include "hw/char/parallel.h"
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#include "hw/char/serial.h"
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#include "hw/input/lasips2.h"
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#include "migration/vmstate.h"
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#include "qom/object.h"
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#define TYPE_LASI_CHIP "lasi-chip"
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#define LASI_IRR 0x00 /* RO */
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#define LASI_IMR 0x04
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#define LASI_IPR 0x08
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#define LASI_ICR 0x0c
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#define LASI_IAR 0x10
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#define LASI_PCR 0x0C000 /* LASI Power Control register */
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#define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */
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#define LASI_VER 0x0C008 /* LASI Version Control register */
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#define LASI_IORESET 0x0C00C /* LASI I/O Reset register */
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#define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */
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#define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */
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#define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */
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#define LASI_BIT(x) (1ul << (x))
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#define LASI_IRQ_BITS (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \
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| LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \
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| LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \
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| LASI_BIT(26))
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#define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */
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#define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */
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OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP)
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struct LasiState {
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PCIHostState parent_obj;
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uint32_t irr;
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uint32_t imr;
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uint32_t ipr;
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uint32_t icr;
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uint32_t iar;
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uint32_t errlog;
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uint32_t amr;
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uint32_t rtc;
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time_t rtc_ref;
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MemoryRegion this_mem;
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};
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static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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bool ret = false;
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switch (addr) {
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case LASI_IRR:
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case LASI_IMR:
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case LASI_IPR:
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case LASI_ICR:
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case LASI_IAR:
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case (LASI_LAN_HPA - LASI_HPA):
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case (LASI_LPT_HPA - LASI_HPA):
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case (LASI_UART_HPA - LASI_HPA):
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case (LASI_RTC_HPA - LASI_HPA):
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case LASI_PCR ... LASI_AMR:
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ret = true;
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}
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trace_lasi_chip_mem_valid(addr, ret);
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return ret;
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}
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static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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LasiState *s = opaque;
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MemTxResult ret = MEMTX_OK;
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uint32_t val;
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switch (addr) {
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case LASI_IRR:
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val = s->irr;
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break;
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case LASI_IMR:
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val = s->imr;
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break;
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case LASI_IPR:
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val = s->ipr;
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/* Any read to IPR clears the register. */
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s->ipr = 0;
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break;
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case LASI_ICR:
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val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
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break;
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case LASI_IAR:
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val = s->iar;
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break;
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case (LASI_LAN_HPA - LASI_HPA):
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case (LASI_LPT_HPA - LASI_HPA):
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case (LASI_UART_HPA - LASI_HPA):
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val = 0;
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break;
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case (LASI_RTC_HPA - LASI_HPA):
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val = time(NULL);
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val += s->rtc_ref;
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break;
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case LASI_PCR:
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case LASI_VER: /* only version 0 existed. */
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case LASI_IORESET:
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val = 0;
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break;
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case LASI_ERRLOG:
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val = s->errlog;
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break;
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case LASI_AMR:
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val = s->amr;
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break;
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default:
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/* Controlled by lasi_chip_mem_valid above. */
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g_assert_not_reached();
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}
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trace_lasi_chip_read(addr, val);
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*data = val;
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return ret;
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}
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static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
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uint64_t val, unsigned size,
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MemTxAttrs attrs)
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{
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LasiState *s = opaque;
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trace_lasi_chip_write(addr, val);
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switch (addr) {
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case LASI_IRR:
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/* read-only. */
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break;
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case LASI_IMR:
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s->imr = val;
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if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff))
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qemu_log_mask(LOG_GUEST_ERROR,
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"LASI: tried to set invalid %lx IMR value.\n",
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(unsigned long) val);
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break;
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case LASI_IPR:
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/* Any write to IPR clears the register. */
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s->ipr = 0;
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break;
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case LASI_ICR:
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s->icr = val;
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/* if (val & ICR_TOC_BIT) issue_toc(); */
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break;
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case LASI_IAR:
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s->iar = val;
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break;
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case (LASI_LAN_HPA - LASI_HPA):
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/* XXX: reset LAN card */
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break;
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case (LASI_LPT_HPA - LASI_HPA):
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/* XXX: reset parallel port */
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break;
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case (LASI_UART_HPA - LASI_HPA):
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/* XXX: reset serial port */
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break;
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case (LASI_RTC_HPA - LASI_HPA):
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s->rtc_ref = val - time(NULL);
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break;
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case LASI_PCR:
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if (val == 0x02) /* immediately power off */
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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break;
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case LASI_ERRLOG:
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s->errlog = val;
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break;
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case LASI_VER:
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/* read-only. */
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break;
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case LASI_IORESET:
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break; /* XXX: TODO: Reset various devices. */
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case LASI_AMR:
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s->amr = val;
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break;
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default:
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/* Controlled by lasi_chip_mem_valid above. */
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g_assert_not_reached();
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps lasi_chip_ops = {
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.read_with_attrs = lasi_chip_read_with_attrs,
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.write_with_attrs = lasi_chip_write_with_attrs,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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.accepts = lasi_chip_mem_valid,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static const VMStateDescription vmstate_lasi = {
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.name = "Lasi",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(irr, LasiState),
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VMSTATE_UINT32(imr, LasiState),
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VMSTATE_UINT32(ipr, LasiState),
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VMSTATE_UINT32(icr, LasiState),
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VMSTATE_UINT32(iar, LasiState),
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VMSTATE_UINT32(errlog, LasiState),
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VMSTATE_UINT32(amr, LasiState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void lasi_set_irq(void *opaque, int irq, int level)
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{
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LasiState *s = opaque;
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uint32_t bit = 1u << irq;
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if (level) {
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s->ipr |= bit;
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if (bit & s->imr) {
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uint32_t iar = s->iar;
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s->irr |= bit;
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if ((s->icr & ICR_BUS_ERROR_BIT) == 0) {
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stl_be_phys(&address_space_memory, iar & -32, iar & 31);
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}
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}
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}
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}
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static int lasi_get_irq(unsigned long hpa)
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{
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switch (hpa) {
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case LASI_HPA:
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return 14;
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case LASI_UART_HPA:
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return 5;
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case LASI_LPT_HPA:
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return 7;
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case LASI_LAN_HPA:
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return 8;
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case LASI_SCSI_HPA:
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return 9;
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case LASI_AUDIO_HPA:
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return 13;
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case LASI_PS2KBD_HPA:
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case LASI_PS2MOU_HPA:
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return 26;
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default:
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g_assert_not_reached();
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}
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}
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DeviceState *lasi_init(MemoryRegion *address_space)
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{
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DeviceState *dev;
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LasiState *s;
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dev = qdev_new(TYPE_LASI_CHIP);
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s = LASI_CHIP(dev);
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s->iar = CPU_HPA + 3;
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/* Lasi access from main memory. */
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memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
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s, "lasi", 0x100000);
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memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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/* LAN */
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if (enable_lasi_lan()) {
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qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s,
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lasi_get_irq(LASI_LAN_HPA));
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lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq);
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}
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/* Parallel port */
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qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s,
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lasi_get_irq(LASI_LPT_HPA));
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parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0,
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lpt_irq, parallel_hds[0]);
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/* Real time clock (RTC), it's only one 32-bit counter @9000 */
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s->rtc = time(NULL);
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s->rtc_ref = 0;
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if (serial_hd(1)) {
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/* Serial port */
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qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s,
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lasi_get_irq(LASI_UART_HPA));
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serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0,
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serial_irq, 8000000 / 16,
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serial_hd(0), DEVICE_NATIVE_ENDIAN);
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}
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/* PS/2 Keyboard/Mouse */
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qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s,
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lasi_get_irq(LASI_PS2KBD_HPA));
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lasips2_init(address_space, LASI_PS2KBD_HPA, ps2kbd_irq);
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return dev;
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}
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static void lasi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_lasi;
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}
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static const TypeInfo lasi_pcihost_info = {
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.name = TYPE_LASI_CHIP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LasiState),
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.class_init = lasi_class_init,
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};
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static void lasi_register_types(void)
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{
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type_register_static(&lasi_pcihost_info);
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}
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type_init(lasi_register_types)
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