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Currently SPAPR PHB keeps track of all allocated MSI (here and below MSI stands for both MSI and MSIX) interrupt because XICS used to be unable to reuse interrupts. This is a problem for dynamic MSI reconfiguration which happens when guest reloads a driver or performs PCI hotplug. Another problem is that the existing implementation can enable MSI on 32 devices maximum (SPAPR_MSIX_MAX_DEVS=32) and there is no good reason for that. This makes use of new XICS ability to reuse interrupts. This reorganizes MSI information storage in sPAPRPHBState. Instead of static array of 32 descriptors (one per a PCI function), this patch adds a GHashTable when @config_addr is a key and (first_irq, num) pair is a value. GHashTable can dynamically grow and shrink so the initial limit of 32 devices is gone. This changes migration stream as @msi_table was a static array while new @msi_devs is a dynamic hash table. This adds temporary array which is used for migration, it is populated in "spapr_pci"::pre_save() callback and expanded into the hash table in post_load() callback. Since the destination side does not know the number of MSI-enabled devices in advance and cannot pre-allocate the temporary array to receive migration state, this makes use of new VMSTATE_STRUCT_VARRAY_ALLOC macro which allocates the array automatically. This resets the MSI configuration space when interrupts are released by the ibm,change-msi RTAS call. This fixed traces to be more informative. This changes vmstate_spapr_pci_msi name from "...lsi" to "...msi" which was incorrect by accident. As the internal representation changed, thus bumps migration version number. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: drop g_malloc_n usage] Signed-off-by: Alexander Graf <agraf@suse.de>
126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
/*
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* QEMU SPAPR PCI BUS definitions
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*
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* Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined(__HW_SPAPR_H__)
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#error Please include spapr.h before this file!
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#endif
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#if !defined(__HW_SPAPR_PCI_H__)
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#define __HW_SPAPR_PCI_H__
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/xics.h"
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#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
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#define TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE "spapr-pci-vfio-host-bridge"
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#define SPAPR_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
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#define SPAPR_PCI_VFIO_HOST_BRIDGE(obj) \
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OBJECT_CHECK(sPAPRPHBVFIOState, (obj), TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE)
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#define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \
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OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE)
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#define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
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typedef struct sPAPRPHBClass sPAPRPHBClass;
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typedef struct sPAPRPHBState sPAPRPHBState;
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typedef struct sPAPRPHBVFIOState sPAPRPHBVFIOState;
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struct sPAPRPHBClass {
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PCIHostBridgeClass parent_class;
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void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
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};
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typedef struct spapr_pci_msi {
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uint32_t first_irq;
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uint32_t num;
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} spapr_pci_msi;
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typedef struct spapr_pci_msi_mig {
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uint32_t key;
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spapr_pci_msi value;
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} spapr_pci_msi_mig;
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struct sPAPRPHBState {
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PCIHostState parent_obj;
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int32_t index;
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uint64_t buid;
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char *dtbusname;
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MemoryRegion memspace, iospace;
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hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
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MemoryRegion memwindow, iowindow;
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uint32_t dma_liobn;
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AddressSpace iommu_as;
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MemoryRegion iommu_root;
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struct spapr_pci_lsi {
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uint32_t irq;
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} lsi_table[PCI_NUM_PINS];
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GHashTable *msi;
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/* Temporary cache for migration purposes */
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int32_t msi_devs_num;
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spapr_pci_msi_mig *msi_devs;
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QLIST_ENTRY(sPAPRPHBState) list;
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};
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struct sPAPRPHBVFIOState {
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sPAPRPHBState phb;
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int32_t iommugroupid;
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};
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#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
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#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
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#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
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#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
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#define SPAPR_PCI_MMIO_WIN_SIZE 0x20000000
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#define SPAPR_PCI_IO_WIN_OFF 0x80000000
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
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{
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return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
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}
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PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index);
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int spapr_populate_pci_dt(sPAPRPHBState *phb,
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uint32_t xics_phandle,
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void *fdt);
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void spapr_pci_msi_init(sPAPREnvironment *spapr, hwaddr addr);
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void spapr_pci_rtas_init(void);
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#endif /* __HW_SPAPR_PCI_H__ */
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