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d2fd9612ee
This is largy inspired by sPAPRCPUCore with some simplification, no hotplug for instance. A set of PnvCore objects is added to the PnvChip and the device tree is populated looping on these cores. Real HW cpu ids are now generated depending on the chip cpu model, the chip id and a core mask. The id is propagated to the CPU object, using properties, to set the SPR_PIR (Processor Identification Register) Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
110 lines
3.1 KiB
C
110 lines
3.1 KiB
C
/*
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* QEMU PowerPC PowerNV various definitions
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*
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* Copyright (c) 2014-2016 BenH, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PPC_PNV_H
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#define _PPC_PNV_H
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#define TYPE_PNV_CHIP "powernv-chip"
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#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
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#define PNV_CHIP_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
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#define PNV_CHIP_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
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typedef enum PnvChipType {
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PNV_CHIP_POWER8E, /* AKA Murano (default) */
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PNV_CHIP_POWER8, /* AKA Venice */
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PNV_CHIP_POWER8NVL, /* AKA Naples */
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PNV_CHIP_POWER9, /* AKA Nimbus */
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} PnvChipType;
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typedef struct PnvChip {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t chip_id;
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uint64_t ram_start;
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uint64_t ram_size;
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uint32_t nr_cores;
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uint64_t cores_mask;
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void *cores;
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} PnvChip;
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typedef struct PnvChipClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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const char *cpu_model;
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PnvChipType chip_type;
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uint64_t chip_cfam_id;
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uint64_t cores_mask;
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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} PnvChipClass;
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#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
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#define PNV_CHIP_POWER8E(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
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#define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8"
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#define PNV_CHIP_POWER8(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
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#define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL"
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#define PNV_CHIP_POWER8NVL(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
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#define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9"
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#define PNV_CHIP_POWER9(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
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/*
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* This generates a HW chip id depending on an index:
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*
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* 0x0, 0x1, 0x10, 0x11
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*
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* 4 chips should be the maximum
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*/
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#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
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#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv")
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#define POWERNV_MACHINE(obj) \
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OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)
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typedef struct PnvMachineState {
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/*< private >*/
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MachineState parent_obj;
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uint32_t initrd_base;
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long initrd_size;
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uint32_t num_chips;
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PnvChip **chips;
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} PnvMachineState;
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#define PNV_FDT_ADDR 0x01000000
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#define PNV_TIMEBASE_FREQ 512000000ULL
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#endif /* _PPC_PNV_H */
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