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Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be corrupted if the UARTRSR is ever written. Fix by implementing a correct model of the UARTRSR/UARTECR register. Reads of this register simply reflect the error bits in data register. Only breaks can be triggered in QEMU. With the pl011_can_receive function, we effectively have flow control between the host and the model. Framing and parity errors simply don't make sense in the model and will never occur. Signed-off-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1395166721-15716-3-git-send-email-robherring2@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| cadence_uart.c | ||
| debugcon.c | ||
| digic-uart.c | ||
| escc.c | ||
| etraxfs_ser.c | ||
| exynos4210_uart.c | ||
| grlib_apbuart.c | ||
| imx_serial.c | ||
| ipoctal232.c | ||
| lm32_juart.c | ||
| lm32_uart.c | ||
| Makefile.objs | ||
| mcf_uart.c | ||
| milkymist-uart.c | ||
| omap_uart.c | ||
| parallel.c | ||
| pl011.c | ||
| sclpconsole-lm.c | ||
| sclpconsole.c | ||
| serial-isa.c | ||
| serial-pci.c | ||
| serial.c | ||
| sh_serial.c | ||
| spapr_vty.c | ||
| virtio-console.c | ||
| virtio-serial-bus.c | ||
| xen_console.c | ||
| xilinx_uartlite.c | ||