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d9bcb58a12
Create a hook in which to split out the mips and sh4 ifdefs from cpu_io_recompile. [AJB: s/stoped/stopped/] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-3-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-12-alex.bennee@linaro.org>
107 lines
4.0 KiB
C
107 lines
4.0 KiB
C
/*
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* TCG CPU-specific operations
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*
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* Copyright 2021 SUSE LLC
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef TCG_CPU_OPS_H
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#define TCG_CPU_OPS_H
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#include "hw/core/cpu.h"
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struct TCGCPUOps {
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/**
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* @initialize: Initalize TCG state
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*
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* Called when the first CPU is realized.
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*/
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void (*initialize)(void);
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/**
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* @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
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*
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* This is called when we abandon execution of a TB before starting it,
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* and must set all parts of the CPU state which the previous TB in the
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* chain may not have updated.
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* By default, when this is NULL, a call is made to @set_pc(tb->pc).
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*
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* If more state needs to be restored, the target must implement a
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* function to restore all the state, and register it here.
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*/
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void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
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/** @cpu_exec_enter: Callback for cpu_exec preparation */
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void (*cpu_exec_enter)(CPUState *cpu);
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/** @cpu_exec_exit: Callback for cpu_exec cleanup */
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void (*cpu_exec_exit)(CPUState *cpu);
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/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
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bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
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/**
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* @do_interrupt: Callback for interrupt handling.
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*
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* note that this is in general SOFTMMU only, but it actually isn't
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* because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it
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* in the SOFTMMU section in general.
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*/
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void (*do_interrupt)(CPUState *cpu);
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/**
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* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
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*
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* For system mode, if the access is valid, call tlb_set_page
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* and return true; if the access is invalid, and probe is
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* true, return false; otherwise raise an exception and do
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* not return. For user-only mode, always raise an exception
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* and do not return.
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*/
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bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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/** @debug_excp_handler: Callback for handling debug exceptions */
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void (*debug_excp_handler)(CPUState *cpu);
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#ifdef NEED_CPU_H
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#ifdef CONFIG_SOFTMMU
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/**
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* @do_transaction_failed: Callback for handling failed memory transactions
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* (ie bus faults or external aborts; not MMU faults)
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*/
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void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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/**
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* @do_unaligned_access: Callback for unaligned access handling
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*/
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void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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/**
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* @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
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*/
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vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
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/**
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* @debug_check_watchpoint: return true if the architectural
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* watchpoint whose address has matched should really fire, used by ARM
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*/
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bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
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/**
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* @io_recompile_replay_branch: Callback for cpu_io_recompile.
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*
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* The cpu has been stopped, and cpu_restore_state_from_tb has been
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* called. If the faulting instruction is in a delay slot, and the
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* target architecture requires re-execution of the branch, then
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* adjust the cpu state as required and return true.
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*/
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bool (*io_recompile_replay_branch)(CPUState *cpu,
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const TranslationBlock *tb);
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#endif /* CONFIG_SOFTMMU */
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#endif /* NEED_CPU_H */
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};
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#endif /* TCG_CPU_OPS_H */
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