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		83fcaefd9d
		
	
	
	
	
		
			
			We add common helper routines which can be shared by RISC-V multi-socket NUMA machines. We have two types of helpers: 1. riscv_socket_xyz() - These helper assist managing multiple sockets irrespective whether QEMU NUMA is enabled/disabled 2. riscv_numa_xyz() - These helpers assist in providing necessary QEMU machine callbacks for QEMU NUMA emulation Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
		
			
				
	
	
		
			114 lines
		
	
	
		
			3.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			114 lines
		
	
	
		
			3.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * QEMU RISC-V NUMA Helper
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|  *
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|  * Copyright (c) 2020 Western Digital Corporation or its affiliates.
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|  *
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|  * This program is free software; you can redistribute it and/or modify it
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|  * under the terms and conditions of the GNU General Public License,
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|  * version 2 or later, as published by the Free Software Foundation.
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|  *
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|  * This program is distributed in the hope it will be useful, but WITHOUT
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|  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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|  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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|  * more details.
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|  *
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|  * You should have received a copy of the GNU General Public License along with
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|  * this program.  If not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #ifndef RISCV_NUMA_H
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| #define RISCV_NUMA_H
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| 
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| #include "hw/sysbus.h"
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| #include "sysemu/numa.h"
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| 
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| /**
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|  * riscv_socket_count:
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|  * @ms: pointer to machine state
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|  *
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|  * Returns: number of sockets for a numa system and 1 for a non-numa system
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|  */
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| int riscv_socket_count(const MachineState *ms);
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| 
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| /**
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|  * riscv_socket_first_hartid:
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|  * @ms: pointer to machine state
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|  * @socket_id: socket index
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|  *
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|  * Returns: first hartid for a valid socket and -1 for an invalid socket
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|  */
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| int riscv_socket_first_hartid(const MachineState *ms, int socket_id);
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| 
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| /**
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|  * riscv_socket_last_hartid:
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|  * @ms: pointer to machine state
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|  * @socket_id: socket index
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|  *
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|  * Returns: last hartid for a valid socket and -1 for an invalid socket
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|  */
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| int riscv_socket_last_hartid(const MachineState *ms, int socket_id);
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| 
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| /**
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|  * riscv_socket_hart_count:
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|  * @ms: pointer to machine state
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|  * @socket_id: socket index
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|  *
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|  * Returns: number of harts for a valid socket and -1 for an invalid socket
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|  */
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| int riscv_socket_hart_count(const MachineState *ms, int socket_id);
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| 
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| /**
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|  * riscv_socket_mem_offset:
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|  * @ms: pointer to machine state
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|  * @socket_id: socket index
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|  *
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|  * Returns: offset of ram belonging to given socket
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|  */
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| uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id);
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| 
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| /**
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|  * riscv_socket_mem_size:
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|  * @ms: pointer to machine state
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|  * @socket_id: socket index
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|  *
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|  * Returns: size of ram belonging to given socket
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|  */
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| uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id);
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| 
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| /**
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|  * riscv_socket_check_hartids:
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|  * @ms: pointer to machine state
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|  * @socket_id: socket index
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|  *
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|  * Returns: true if hardids belonging to given socket are contiguous else false
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|  */
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| bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
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| 
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| /**
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|  * riscv_socket_fdt_write_id:
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|  * @ms: pointer to machine state
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|  * @socket_id: socket index
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|  *
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|  * Write NUMA node-id FDT property for given FDT node
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|  */
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| void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
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|                                const char *node_name, int socket_id);
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| 
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| /**
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|  * riscv_socket_fdt_write_distance_matrix:
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|  * @ms: pointer to machine state
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|  * @socket_id: socket index
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|  *
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|  * Write NUMA distance matrix in FDT for given machine
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|  */
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| void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt);
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| 
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| CpuInstanceProperties
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| riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);
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| 
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| int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx);
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| 
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| const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms);
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| 
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| #endif /* RISCV_NUMA_H */
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