mirror of
				https://github.com/qemu/qemu.git
				synced 2025-10-31 04:06:46 +00:00 
			
		
		
		
	 feabc71dfa
			
		
	
	
		feabc71dfa
		
	
	
	
	
		
			
			All Meson executables should specify their dependencies explicitly, either directly or indirectly via declare_dependency. Makefiles instead did not propagate dependencies correctly from static libraries, for example. Therefore, flags for dependencies need not be included in QEMU_CFLAGS. LIBS is not used at all, so drop that one as well. In a few cases the dependencies were not yet specified, so add them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
		
			
				
	
	
		
			21 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			Meson
		
	
	
	
	
	
			
		
		
	
	
			21 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			Meson
		
	
	
	
	
	
| riscv_ss = ss.source_set()
 | |
| riscv_ss.add(files('boot.c'), fdt)
 | |
| riscv_ss.add(files('numa.c'))
 | |
| riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 | |
| riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 | |
| riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 | |
| riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 | |
| 
 | |
| hw_arch += {'riscv': riscv_ss}
 |