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e4bcb14c79
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3759 c046a42c-6fe2-441c-8c8c-71466251a162
374 lines
13 KiB
C
374 lines
13 KiB
C
/*
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* QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "ppc.h"
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#include "ppc_mac.h"
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#include "nvram.h"
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#include "pc.h"
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#include "sysemu.h"
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#include "net.h"
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#include "isa.h"
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#include "pci.h"
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#include "boards.h"
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#define MAX_IDE_BUS 2
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/* temporary frame buffer OSI calls for the video.x driver. The right
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solution is to modify the driver to use VGA PCI I/Os */
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/* XXX: to be removed. This is no way related to emulation */
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static int vga_osi_call (CPUState *env)
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{
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static int vga_vbl_enabled;
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int linesize;
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// printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
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/* same handler as PearPC, coming from the original MOL video
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driver. */
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switch(env->gpr[5]) {
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case 4:
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break;
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case 28: /* set_vmode */
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if (env->gpr[6] != 1 || env->gpr[7] != 0)
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env->gpr[3] = 1;
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else
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env->gpr[3] = 0;
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break;
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case 29: /* get_vmode_info */
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if (env->gpr[6] != 0) {
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if (env->gpr[6] != 1 || env->gpr[7] != 0) {
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env->gpr[3] = 1;
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break;
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}
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}
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env->gpr[3] = 0;
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env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
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env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
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env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
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env->gpr[7] = 85 << 16; /* refresh rate */
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env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
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linesize = ((graphic_depth + 7) >> 3) * graphic_width;
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linesize = (linesize + 3) & ~3;
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env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
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break;
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case 31: /* set_video power */
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env->gpr[3] = 0;
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break;
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case 39: /* video_ctrl */
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if (env->gpr[6] == 0 || env->gpr[6] == 1)
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vga_vbl_enabled = env->gpr[6];
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env->gpr[3] = 0;
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break;
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case 47:
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break;
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case 59: /* set_color */
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/* R6 = index, R7 = RGB */
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env->gpr[3] = 0;
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break;
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case 64: /* get color */
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/* R6 = index */
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env->gpr[3] = 0;
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break;
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case 116: /* set hwcursor */
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/* R6 = x, R7 = y, R8 = visible, R9 = data */
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break;
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default:
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fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
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ppc_dump_gpr(env, 5));
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break;
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}
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return 1; /* osi_call handled */
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}
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static void ppc_heathrow_init (int ram_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model)
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{
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CPUState *env = NULL, *envs[MAX_CPUS];
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char buf[1024];
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qemu_irq *pic, **heathrow_irqs;
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nvram_t nvram;
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m48t59_t *m48t59;
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int linux_boot, i;
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unsigned long bios_offset, vga_bios_offset;
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
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PCIBus *pci_bus;
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MacIONVRAMState *nvr;
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int vga_bios_size, bios_size;
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qemu_irq *dummy_irq;
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int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
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int ide_mem_index[2];
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int ppc_boot_device;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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int index;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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if (cpu_model == NULL)
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cpu_model = "default";
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for (i = 0; i < smp_cpus; i++) {
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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exit(1);
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}
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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env->osi_call = vga_osi_call;
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qemu_register_reset(&cpu_ppc_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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envs[i] = env;
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}
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if (env->nip < 0xFFF80000) {
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/* Special test for PowerPC 601:
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* the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
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* But the NVRAM is located at 0xFFF04000...
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*/
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cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
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}
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* allocate and load BIOS */
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bios_offset = ram_size + vga_ram_size;
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
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exit(1);
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}
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bios_size = (bios_size + 0xfff) & ~0xfff;
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if (bios_size > 0x00080000) {
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/* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
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cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
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}
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cpu_register_physical_memory((uint32_t)(-bios_size),
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bios_size, bios_offset | IO_MEM_ROM);
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/* allocate and load VGA BIOS */
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vga_bios_offset = bios_offset + bios_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
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vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
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if (vga_bios_size < 0) {
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/* if no bios is present, we can still work */
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fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
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vga_bios_size = 0;
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} else {
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/* set a specific header (XXX: find real Apple format for NDRV
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drivers) */
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phys_ram_base[vga_bios_offset] = 'N';
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phys_ram_base[vga_bios_offset + 1] = 'D';
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phys_ram_base[vga_bios_offset + 2] = 'R';
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phys_ram_base[vga_bios_offset + 3] = 'V';
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cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
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vga_bios_size);
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vga_bios_size += 8;
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}
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vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR;
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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if (kernel_size < 0) {
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cpu_abort(env, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR;
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initrd_size = load_image(initrd_filename,
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phys_ram_base + initrd_base);
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if (initrd_size < 0) {
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cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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} else {
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initrd_base = 0;
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initrd_size = 0;
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}
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ppc_boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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ppc_boot_device = '\0';
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for (i = 0; boot_device[i] != '\0'; i++) {
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/* TOFIX: for now, the second IDE channel is not properly
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* used by OHW. The Mac floppy disk are not emulated.
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* For now, OHW cannot boot from the network.
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*/
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#if 0
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if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
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ppc_boot_device = boot_device[i];
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break;
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}
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#else
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if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
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ppc_boot_device = boot_device[i];
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break;
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}
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#endif
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}
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if (ppc_boot_device == '\0') {
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fprintf(stderr, "No valid boot device for Mac99 machine\n");
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exit(1);
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}
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}
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isa_mem_base = 0x80000000;
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/* Register 2 MB of ISA IO space */
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isa_mmio_init(0xfe000000, 0x00200000);
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/* XXX: we register only 1 output pin for heathrow PIC */
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heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
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heathrow_irqs[0] =
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qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
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/* Connect the heathrow PIC outputs to the 6xx bus */
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for (i = 0; i < smp_cpus; i++) {
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_6xx:
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heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
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heathrow_irqs[i][0] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
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break;
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default:
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cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
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exit(1);
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}
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}
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/* init basic PC hardware */
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if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
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cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
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exit(1);
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}
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pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
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pci_bus = pci_grackle_init(0xfec00000, pic);
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pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
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ram_size, vga_ram_size,
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vga_bios_offset, vga_bios_size);
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/* XXX: suppress that */
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dummy_irq = i8259_init(NULL);
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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if (!nd_table[i].model)
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nd_table[i].model = "ne2k_pci";
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pci_nic_init(pci_bus, &nd_table[i], -1);
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}
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/* First IDE channel is a CMD646 on the PCI bus */
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if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
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fprintf(stderr, "qemu: too many IDE bus\n");
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exit(1);
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}
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index = drive_get_index(IF_IDE, 0, 0);
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if (index == -1)
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hd[0] = NULL;
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else
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hd[0] = drives_table[index].bdrv;
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index = drive_get_index(IF_IDE, 0, 1);
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if (index == -1)
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hd[1] = NULL;
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else
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hd[1] = drives_table[index].bdrv;
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hd[3] = hd[2] = NULL;
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pci_cmd646_ide_init(pci_bus, hd, 0);
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/* Second IDE channel is a MAC IDE on the MacIO bus */
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index = drive_get_index(IF_IDE, 1, 0);
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if (index == -1)
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hd[0] = NULL;
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else
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hd[0] = drives_table[index].bdrv;
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index = drive_get_index(IF_IDE, 1, 1);
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if (index == -1)
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hd[1] = NULL;
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else
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hd[1] = drives_table[index].bdrv;
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ide_mem_index[0] = -1;
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ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);
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/* cuda also initialize ADB */
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cuda_init(&cuda_mem_index, pic[0x12]);
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adb_kbd_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
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pmac_format_nvram_partition(nvr, 0x2000);
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dbdma_init(&dbdma_mem_index);
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macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
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cuda_mem_index, nvr, 2, ide_mem_index);
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if (usb_enabled) {
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usb_ohci_init_pci(pci_bus, 3, -1);
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}
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if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
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graphic_depth = 15;
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m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
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nvram.opaque = m48t59;
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nvram.read_fn = &m48t59_read;
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nvram.write_fn = &m48t59_write;
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PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
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ppc_boot_device, kernel_base, kernel_size,
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kernel_cmdline,
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initrd_base, initrd_size,
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/* XXX: need an option to load a NVRAM image */
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0,
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graphic_width, graphic_height, graphic_depth);
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/* No PCI init: the BIOS will do it */
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/* Special port to get debug messages from Open-Firmware */
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register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
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}
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QEMUMachine heathrow_machine = {
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"g3bw",
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"Heathrow based PowerMAC",
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ppc_heathrow_init,
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};
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