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e4bcb14c79
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3759 c046a42c-6fe2-441c-8c8c-71466251a162
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
#ifndef QEMU_PCI_H
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#define QEMU_PCI_H
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/* PCI includes legacy ISA access. */
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#include "isa.h"
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/* PCI bus */
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extern target_phys_addr_t pci_mem_base;
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typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
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uint32_t address, uint32_t data, int len);
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typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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uint32_t address, int len);
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typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type);
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#define PCI_ADDRESS_SPACE_MEM 0x00
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#define PCI_ADDRESS_SPACE_IO 0x01
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#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
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typedef struct PCIIORegion {
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uint32_t addr; /* current PCI mapping address. -1 means not mapped */
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uint32_t size;
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uint8_t type;
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PCIMapIORegionFunc *map_func;
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} PCIIORegion;
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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#define PCI_DEVICES_MAX 64
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MAX_LAT 0x3f /* 8 bits */
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struct PCIDevice {
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/* PCI config space */
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uint8_t config[256];
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/* the following fields are read only */
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PCIBus *bus;
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int devfn;
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char name[64];
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PCIIORegion io_regions[PCI_NUM_REGIONS];
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/* do not access the following fields */
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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/* ??? This is a PC-specific hack, and should be removed. */
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int irq_index;
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/* IRQ objects for the INTA-INTD pins. */
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qemu_irq *irq;
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/* Current IRQ levels. Used internally by the generic PCI code. */
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int irq_state[4];
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};
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PCIDevice *pci_register_device(PCIBus *bus, const char *name,
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int instance_size, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write);
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void pci_register_io_region(PCIDevice *pci_dev, int region_num,
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func);
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uint32_t pci_default_read_config(PCIDevice *d,
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uint32_t address, int len);
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len);
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void pci_device_save(PCIDevice *s, QEMUFile *f);
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int pci_device_load(PCIDevice *s, QEMUFile *f);
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typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
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typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
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PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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qemu_irq *pic, int devfn_min, int nirq);
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void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
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void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
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uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
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int pci_bus_num(PCIBus *s);
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void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
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void pci_info(void);
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PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
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pci_map_irq_fn map_irq, const char *name);
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/* lsi53c895a.c */
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#define LSI_MAX_DEVS 7
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void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
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void *lsi_scsi_init(PCIBus *bus, int devfn);
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/* vmware_vga.c */
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void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
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unsigned long vga_ram_offset, int vga_ram_size);
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/* usb-uhci.c */
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void usb_uhci_piix3_init(PCIBus *bus, int devfn);
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void usb_uhci_piix4_init(PCIBus *bus, int devfn);
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/* usb-ohci.c */
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void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
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/* eepro100.c */
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void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
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void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
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void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
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/* ne2000.c */
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void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
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/* rtl8139.c */
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void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
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/* pcnet.c */
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void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
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/* prep_pci.c */
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PCIBus *pci_prep_init(qemu_irq *pic);
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/* apb_pci.c */
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PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
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qemu_irq *pic);
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#endif
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