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c27a5ba948
The Interrupt Group Registers allow the guest to configure interrupts into one of two groups, where Group0 are higher priority and may be routed to IRQ or FIQ, and Group1 are lower priority and always routed to IRQ. (In a GIC with the security extensions Group0 is Secure interrupts and Group 1 is NonSecure.) The GICv2 always supports interrupt grouping; the GICv1 does only if it implements the security extensions. This patch implements the ability to read and write the registers; the actual functionality the bits control will be added in a subsequent patch. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-5-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-7-git-send-email-greg.bellows@linaro.org [PMM: bring GIC_*_GROUP macros into line with the others, ie a simple SET/CLEAR/TEST rather than GROUP0/GROUP1; utility gic_has_groups() function; minor style fixes; bump vmstate version] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| allwinner-a10-pic.c | ||
| apic_common.c | ||
| apic.c | ||
| arm_gic_common.c | ||
| arm_gic_kvm.c | ||
| arm_gic.c | ||
| armv7m_nvic.c | ||
| etraxfs_pic.c | ||
| exynos4210_combiner.c | ||
| exynos4210_gic.c | ||
| gic_internal.h | ||
| grlib_irqmp.c | ||
| heathrow_pic.c | ||
| i8259_common.c | ||
| i8259.c | ||
| imx_avic.c | ||
| ioapic_common.c | ||
| ioapic.c | ||
| lm32_pic.c | ||
| Makefile.objs | ||
| omap_intc.c | ||
| openpic_kvm.c | ||
| openpic.c | ||
| pl190.c | ||
| puv3_intc.c | ||
| realview_gic.c | ||
| s390_flic_kvm.c | ||
| s390_flic.c | ||
| sh_intc.c | ||
| slavio_intctl.c | ||
| xics_kvm.c | ||
| xics.c | ||
| xilinx_intc.c | ||