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This provides to a PowerNV chip (POWER8) access to the Interrupt Management area, which contains the registers of the Interrupt Control Presenters of each thread. These are used to accept, return, forward interrupts in the system. This area is modeled with a per-chip container memory region holding all the ICP registers. Each thread of a chip is then associated with its ICP registers using a memory subregion indexed by its PIR number in the overall region. The device tree is populated accordingly. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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| .. | ||
| fdt.h | ||
| mac_dbdma.h | ||
| openpic.h | ||
| pnv_core.h | ||
| pnv_lpc.h | ||
| pnv_xscom.h | ||
| pnv.h | ||
| ppc4xx.h | ||
| ppc_e500.h | ||
| ppc.h | ||
| spapr_cpu_core.h | ||
| spapr_drc.h | ||
| spapr_ovec.h | ||
| spapr_rtas.h | ||
| spapr_vio.h | ||
| spapr.h | ||
| xics.h | ||