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8063396bf3
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
/*
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* Copyright (c) 2017, Impinj, Inc.
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*
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* i.MX2 Watchdog IP block
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef IMX2_WDT_H
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#define IMX2_WDT_H
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#include "qemu/bitops.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/ptimer.h"
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#include "qom/object.h"
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#define TYPE_IMX2_WDT "imx2.wdt"
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OBJECT_DECLARE_SIMPLE_TYPE(IMX2WdtState, IMX2_WDT)
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enum IMX2WdtRegisters {
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IMX2_WDT_WCR = 0x0000, /* Control Register */
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IMX2_WDT_WSR = 0x0002, /* Service Register */
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IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
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IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
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IMX2_WDT_WMCR = 0x0008, /* Misc Register */
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};
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#define IMX2_WDT_MMIO_SIZE 0x000a
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/* Control Register definitions */
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#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */
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#define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */
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#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */
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#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */
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#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */
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#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */
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#define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */
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#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */
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#define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
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| IMX2_WDT_WCR_WDW)
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/* Service Register definitions */
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#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */
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#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */
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/* Reset Status Register definitions */
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#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */
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#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */
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/* Interrupt Control Register definitions */
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#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */
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#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */
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#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */
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#define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */
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#define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
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/* Misc Control Register definitions */
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#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */
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struct IMX2WdtState {
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/* <private> */
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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qemu_irq irq;
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struct ptimer_state *timer;
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struct ptimer_state *itimer;
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bool pretimeout_support;
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bool wicr_locked;
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uint16_t wcr;
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uint16_t wsr;
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uint16_t wrsr;
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uint16_t wicr;
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uint16_t wmcr;
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bool wcr_locked; /* affects WDZST, WDBG, and WDW */
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bool wcr_wde_locked; /* affects WDE */
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bool wcr_wdt_locked; /* affects WDT (never cleared) */
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};
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#endif /* IMX2_WDT_H */
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