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The NPCM730 and NPCM750 SoCs have three timer modules each holding five timers and some shared registers (e.g. interrupt status). Each timer runs at 25 MHz divided by a prescaler, and counts down from a configurable initial value to zero. When zero is reached, the interrupt flag for the timer is set, and the timer is disabled (one-shot mode) or reloaded from its initial value (periodic mode). This implementation is sufficient to boot a Linux kernel configured for NPCM750. Note that the kernel does not seem to actually turn on the interrupts. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-4-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| a9gtimer.h | ||
| allwinner-a10-pit.h | ||
| arm_mptimer.h | ||
| armv7m_systick.h | ||
| aspeed_timer.h | ||
| avr_timer16.h | ||
| bcm2835_systmr.h | ||
| cmsdk-apb-dualtimer.h | ||
| cmsdk-apb-timer.h | ||
| digic-timer.h | ||
| hpet.h | ||
| i8254_internal.h | ||
| i8254.h | ||
| imx_epit.h | ||
| imx_gpt.h | ||
| mips_gictimer.h | ||
| mss-timer.h | ||
| npcm7xx_timer.h | ||
| nrf51_timer.h | ||
| renesas_cmt.h | ||
| renesas_tmr.h | ||
| stm32f2xx_timer.h | ||
| tmu012.h | ||