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		8110fa1d94
		
	
	
	
	
		
			
			Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
		
			
				
	
	
		
			57 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			57 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Spike machine interface
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|  *
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|  * Copyright (c) 2017 SiFive, Inc.
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|  *
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|  * This program is free software; you can redistribute it and/or modify it
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|  * under the terms and conditions of the GNU General Public License,
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|  * version 2 or later, as published by the Free Software Foundation.
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|  *
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|  * This program is distributed in the hope it will be useful, but WITHOUT
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|  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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|  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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|  * more details.
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|  *
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|  * You should have received a copy of the GNU General Public License along with
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|  * this program.  If not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #ifndef HW_RISCV_SPIKE_H
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| #define HW_RISCV_SPIKE_H
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| 
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| #include "hw/riscv/riscv_hart.h"
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| #include "hw/sysbus.h"
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| #include "qom/object.h"
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| 
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| #define SPIKE_CPUS_MAX 8
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| #define SPIKE_SOCKETS_MAX 8
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| 
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| #define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike")
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| typedef struct SpikeState SpikeState;
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| DECLARE_INSTANCE_CHECKER(SpikeState, SPIKE_MACHINE,
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|                          TYPE_SPIKE_MACHINE)
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| 
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| struct SpikeState {
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|     /*< private >*/
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|     MachineState parent;
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| 
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|     /*< public >*/
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|     RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
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|     void *fdt;
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|     int fdt_size;
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| };
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| 
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| enum {
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|     SPIKE_MROM,
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|     SPIKE_CLINT,
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|     SPIKE_DRAM
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| };
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| 
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| #if defined(TARGET_RISCV32)
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| #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
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| #elif defined(TARGET_RISCV64)
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| #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
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| #endif
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| 
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| #endif
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