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Convert the following Integer Multiply-Accumulate opcodes: * MSAC Multiply, negate, accumulate, and move LO * MSACHI Multiply, negate, accumulate, and move HI * MSACHIU Unsigned multiply, negate, accumulate, and move HI * MSACU Unsigned multiply, negate, accumulate, and move LO Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-8-f4bug@amsat.org>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
/*
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* VR5432 extensions translation routines
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*
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* Reference: VR5432 Microprocessor User’s Manual
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* (Document Number U13751EU5V0UM00)
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*
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* Copyright (c) 2021 Philippe Mathieu-Daudé
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "tcg/tcg-op.h"
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#include "exec/helper-gen.h"
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#include "translate.h"
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#include "internal.h"
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/* Include the auto-generated decoder. */
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#include "decode-vr54xx.c.inc"
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/*
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* Integer Multiply-Accumulate Instructions
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*
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* MACC Multiply, accumulate, and move LO
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* MACCHI Multiply, accumulate, and move HI
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* MACCHIU Unsigned multiply, accumulate, and move HI
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* MACCU Unsigned multiply, accumulate, and move LO
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* MSAC Multiply, negate, accumulate, and move LO
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* MSACHI Multiply, negate, accumulate, and move HI
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* MSACHIU Unsigned multiply, negate, accumulate, and move HI
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* MSACU Unsigned multiply, negate, accumulate, and move LO
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* MULHI Multiply and move HI
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* MULHIU Unsigned multiply and move HI
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* MULS Multiply, negate, and move LO
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* MULSHI Multiply, negate, and move HI
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* MULSHIU Unsigned multiply, negate, and move HI
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* MULSU Unsigned multiply, negate, and move LO
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*/
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static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
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void (*gen_helper_mult_acc)(TCGv, TCGv_ptr, TCGv, TCGv))
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_load_gpr(t0, a->rs);
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gen_load_gpr(t1, a->rt);
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gen_helper_mult_acc(t0, cpu_env, t0, t1);
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gen_store_gpr(t0, a->rd);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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return false;
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}
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TRANS(MACC, trans_mult_acc, gen_helper_macc);
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TRANS(MACCHI, trans_mult_acc, gen_helper_macchi);
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TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu);
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TRANS(MACCU, trans_mult_acc, gen_helper_maccu);
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TRANS(MSAC, trans_mult_acc, gen_helper_msac);
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TRANS(MSACHI, trans_mult_acc, gen_helper_msachi);
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TRANS(MSACHIU, trans_mult_acc, gen_helper_msachiu);
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TRANS(MSACU, trans_mult_acc, gen_helper_msacu);
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TRANS(MULHI, trans_mult_acc, gen_helper_mulhi);
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TRANS(MULHIU, trans_mult_acc, gen_helper_mulhiu);
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TRANS(MULS, trans_mult_acc, gen_helper_muls);
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TRANS(MULSHI, trans_mult_acc, gen_helper_mulshi);
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TRANS(MULSHIU, trans_mult_acc, gen_helper_mulshiu);
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TRANS(MULSU, trans_mult_acc, gen_helper_mulsu);
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