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fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
52 lines
1.9 KiB
Plaintext
52 lines
1.9 KiB
Plaintext
Unsolved issues/bugs in the mips/mipsel backend
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General
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-------
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- Unimplemented ASEs:
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- MDMX
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- SmartMIPS
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- microMIPS DSP r1 & r2 encodings
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- MT ASE only partially implemented and not functional
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- Shadow register support only partially implemented,
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lacks set switching on interrupt/exception.
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- 34K ITC not implemented.
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- A general lack of documentation, especially for technical internals.
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Existing documentation is x86-centric.
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- Reverse endianness bit not implemented
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- The TLB emulation is very inefficient:
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QEMU's softmmu implements a x86-style MMU, with separate entries
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for read/write/execute, a TLB index which is just a modulo of the
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virtual address, and a set of TLBs for each user/kernel/supervisor
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MMU mode.
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MIPS has a single entry for read/write/execute and only one MMU mode.
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But it is fully associative with randomized entry indices, and uses
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up to 256 ASID tags as additional matching criterion (which roughly
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equates to 256 MMU modes). It also has a global flag which causes
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entries to match regardless of ASID.
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To cope with these differences, QEMU currently flushes the TLB at
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each ASID change. Using the MMU modes to implement ASIDs hinges on
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implementing the global bit efficiently.
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- save/restore of the CPU state is not implemented (see machine.c).
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MIPS64
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------
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- Userland emulation (both n32 and n64) not functional.
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"Generic" 4Kc system emulation
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------------------------------
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- Doesn't correspond to any real hardware. Should be removed some day,
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U-Boot is the last remaining user.
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PICA 61 system emulation
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------------------------
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- No framebuffer support yet.
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MALTA system emulation
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----------------------
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- We fake firmware support instead of doing the real thing
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- Real firmware (YAMON) falls over when trying to init RAM, presumably
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due to lacking system controller emulation.
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- Bonito system controller not implemented
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- MSC1 system controller not implemented
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