mirror of
https://github.com/qemu/qemu.git
synced 2025-10-31 12:07:31 +00:00
0694dabe97
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
23 lines
235 B
Plaintext
23 lines
235 B
Plaintext
config PL022
|
|
bool
|
|
select SSI
|
|
|
|
config SIFIVE_SPI
|
|
bool
|
|
select SSI
|
|
|
|
config SSI
|
|
bool
|
|
|
|
config XILINX_SPI
|
|
bool
|
|
select SSI
|
|
|
|
config XILINX_SPIPS
|
|
bool
|
|
select SSI
|
|
|
|
config STM32F2XX_SPI
|
|
bool
|
|
select SSI
|