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Use the Clock API and let the CPU object have an input clock.
If no clock is connected, keep using the default frequency of
200 MHz used since the introduction of the 'r4k' machine in
commit 6af0bf9c7c
.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-12-f4bug@amsat.org>
291 lines
7.9 KiB
C
291 lines
7.9 KiB
C
/*
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* QEMU MIPS CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "internal.h"
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#include "kvm_mips.h"
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#include "qemu/module.h"
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#include "sysemu/kvm.h"
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#include "exec/exec-all.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-clock.h"
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static void mips_cpu_set_pc(CPUState *cs, vaddr value)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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env->active_tc.PC = value & ~(target_ulong)1;
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if (value & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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} else {
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env->hflags &= ~(MIPS_HFLAG_M16);
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}
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}
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static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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env->active_tc.PC = tb->pc;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
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}
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static bool mips_cpu_has_work(CPUState *cs)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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bool has_work = false;
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/*
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* Prior to MIPS Release 6 it is implementation dependent if non-enabled
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* interrupts wake-up the CPU, however most of the implementations only
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* check for interrupts that can be taken.
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*/
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if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_mips_hw_interrupts_pending(env)) {
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if (cpu_mips_hw_interrupts_enabled(env) ||
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(env->insn_flags & ISA_MIPS32R6)) {
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has_work = true;
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}
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}
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/* MIPS-MT has the ability to halt the CPU. */
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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/*
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* The QEMU model will issue an _WAKE request whenever the CPUs
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* should be woken up.
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*/
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if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
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has_work = true;
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}
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if (!mips_vpe_active(env)) {
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has_work = false;
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}
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}
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/* MIPS Release 6 has the ability to halt the CPU. */
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if (env->CP0_Config5 & (1 << CP0C5_VP)) {
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if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
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has_work = true;
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}
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if (!mips_vp_active(env)) {
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has_work = false;
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}
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}
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return has_work;
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}
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static void mips_cpu_reset(DeviceState *dev)
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{
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CPUState *s = CPU(dev);
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MIPSCPU *cpu = MIPS_CPU(s);
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
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CPUMIPSState *env = &cpu->env;
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mcc->parent_reset(dev);
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memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
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cpu_state_reset(env);
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#ifndef CONFIG_USER_ONLY
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if (kvm_enabled()) {
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kvm_mips_reset_vcpu(cpu);
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}
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#endif
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}
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static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
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{
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MIPSCPU *cpu = MIPS_CPU(s);
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CPUMIPSState *env = &cpu->env;
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if (!(env->insn_flags & ISA_NANOMIPS32)) {
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#ifdef TARGET_WORDS_BIGENDIAN
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info->print_insn = print_insn_big_mips;
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#else
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info->print_insn = print_insn_little_mips;
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#endif
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} else {
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#if defined(CONFIG_NANOMIPS_DIS)
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info->print_insn = print_insn_nanomips;
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#endif
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}
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}
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/*
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* Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
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*/
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#define CPU_FREQ_HZ_DEFAULT 200000000
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#define CP0_COUNT_RATE_DEFAULT 2
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static void mips_cp0_period_set(MIPSCPU *cpu)
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{
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CPUMIPSState *env = &cpu->env;
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env->cp0_count_ns = cpu->cp0_count_rate
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* clock_get_ns(MIPS_CPU(cpu)->clock);
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assert(env->cp0_count_ns);
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}
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static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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MIPSCPU *cpu = MIPS_CPU(dev);
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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if (!clock_get(cpu->clock)) {
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/* Initialize the frequency in case the clock remains unconnected. */
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clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
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}
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mips_cp0_period_set(cpu);
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cpu_mips_realize_env(&cpu->env);
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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mcc->parent_realize(dev, errp);
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}
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static void mips_cpu_initfn(Object *obj)
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{
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MIPSCPU *cpu = MIPS_CPU(obj);
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CPUMIPSState *env = &cpu->env;
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
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cpu_set_cpustate_pointers(cpu);
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cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu);
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env->cpu_model = mcc->cpu_def;
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}
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static char *mips_cpu_type_name(const char *cpu_model)
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{
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return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
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}
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static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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typename = mips_cpu_type_name(cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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return oc;
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}
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static Property mips_cpu_properties[] = {
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/* CP0 timer running at half the clock of the CPU */
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DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
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CP0_COUNT_RATE_DEFAULT),
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DEFINE_PROP_END_OF_LIST()
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};
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static void mips_cpu_class_init(ObjectClass *c, void *data)
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{
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MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
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CPUClass *cc = CPU_CLASS(c);
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DeviceClass *dc = DEVICE_CLASS(c);
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device_class_set_parent_realize(dc, mips_cpu_realizefn,
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&mcc->parent_realize);
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device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
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device_class_set_props(dc, mips_cpu_properties);
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cc->class_by_name = mips_cpu_class_by_name;
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cc->has_work = mips_cpu_has_work;
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cc->do_interrupt = mips_cpu_do_interrupt;
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cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
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cc->dump_state = mips_cpu_dump_state;
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cc->set_pc = mips_cpu_set_pc;
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cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
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cc->gdb_read_register = mips_cpu_gdb_read_register;
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cc->gdb_write_register = mips_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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cc->do_transaction_failed = mips_cpu_do_transaction_failed;
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cc->do_unaligned_access = mips_cpu_do_unaligned_access;
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cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
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cc->vmsd = &vmstate_mips_cpu;
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#endif
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cc->disas_set_info = mips_cpu_disas_set_info;
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#ifdef CONFIG_TCG
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cc->tcg_initialize = mips_tcg_init;
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cc->tlb_fill = mips_cpu_tlb_fill;
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#endif
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cc->gdb_num_core_regs = 73;
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cc->gdb_stop_before_watchpoint = true;
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}
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static const TypeInfo mips_cpu_type_info = {
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.name = TYPE_MIPS_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(MIPSCPU),
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.instance_init = mips_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(MIPSCPUClass),
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.class_init = mips_cpu_class_init,
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};
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static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
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{
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MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
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mcc->cpu_def = data;
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}
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static void mips_register_cpudef_type(const struct mips_def_t *def)
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{
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char *typename = mips_cpu_type_name(def->name);
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TypeInfo ti = {
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.name = typename,
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.parent = TYPE_MIPS_CPU,
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.class_init = mips_cpu_cpudef_class_init,
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.class_data = (void *)def,
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};
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type_register(&ti);
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g_free(typename);
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}
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static void mips_cpu_register_types(void)
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{
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int i;
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type_register_static(&mips_cpu_type_info);
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for (i = 0; i < mips_defs_number; i++) {
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mips_register_cpudef_type(&mips_defs[i]);
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}
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}
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type_init(mips_cpu_register_types)
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