qemu/include/hw/riscv
Bin Meng 9a2551ed6f
riscv: sifive_test: Add reset functionality
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17 08:42:44 -07:00
..
boot.h riscv: Add a helper routine for finding firmware 2019-09-17 08:42:43 -07:00
riscv_hart.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
riscv_htif.h Clean up inclusion of sysemu/sysemu.h 2019-08-16 13:31:53 +02:00
sifive_clint.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
sifive_e.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
sifive_gpio.h SiFive RISC-V GPIO Device 2019-05-24 11:58:30 -07:00
sifive_plic.h riscv: plic: Remove unused interrupt functions 2019-09-17 08:42:42 -07:00
sifive_prci.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
sifive_test.h riscv: sifive_test: Add reset functionality 2019-09-17 08:42:44 -07:00
sifive_u.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
sifive_uart.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
spike.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
virt.h include: Make headers more self-contained 2019-08-16 13:31:51 +02:00