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73f6ed97ac
Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
207 lines
8.3 KiB
C
207 lines
8.3 KiB
C
/*
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* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
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*
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* Copyright (c) 2020 Western Digital
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*
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* Provides a board compatible with the OpenTitan FPGA platform:
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/riscv/opentitan.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/misc/unimp.h"
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#include "hw/riscv/boot.h"
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#include "exec/address-spaces.h"
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#include "qemu/units.h"
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#include "sysemu/sysemu.h"
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} ibex_memmap[] = {
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[IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
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[IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
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[IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
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[IBEX_DEV_UART] = { 0x40000000, 0x10000 },
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[IBEX_DEV_GPIO] = { 0x40010000, 0x10000 },
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[IBEX_DEV_SPI] = { 0x40020000, 0x10000 },
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[IBEX_DEV_FLASH_CTRL] = { 0x40030000, 0x10000 },
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[IBEX_DEV_PINMUX] = { 0x40070000, 0x10000 },
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[IBEX_DEV_RV_TIMER] = { 0x40080000, 0x10000 },
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[IBEX_DEV_PLIC] = { 0x40090000, 0x10000 },
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[IBEX_DEV_PWRMGR] = { 0x400A0000, 0x10000 },
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[IBEX_DEV_RSTMGR] = { 0x400B0000, 0x10000 },
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[IBEX_DEV_CLKMGR] = { 0x400C0000, 0x10000 },
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[IBEX_DEV_AES] = { 0x40110000, 0x10000 },
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[IBEX_DEV_HMAC] = { 0x40120000, 0x10000 },
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[IBEX_DEV_ALERT_HANDLER] = { 0x40130000, 0x10000 },
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[IBEX_DEV_NMI_GEN] = { 0x40140000, 0x10000 },
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[IBEX_DEV_USBDEV] = { 0x40150000, 0x10000 },
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[IBEX_DEV_PADCTRL] = { 0x40160000, 0x10000 }
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};
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static void opentitan_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = ibex_memmap;
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OpenTitanState *s = g_new0(OpenTitanState, 1);
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MemoryRegion *sys_mem = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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/* Initialize SoC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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TYPE_RISCV_IBEX_SOC);
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qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
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memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
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memmap[IBEX_DEV_RAM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[IBEX_DEV_RAM].base, main_mem);
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if (machine->firmware) {
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riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
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}
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if (machine->kernel_filename) {
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riscv_load_kernel(machine->kernel_filename, NULL);
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}
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}
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static void opentitan_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Board compatible with OpenTitan";
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mc->init = opentitan_board_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
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}
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DEFINE_MACHINE("opentitan", opentitan_machine_init)
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static void lowrisc_ibex_soc_init(Object *obj)
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{
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LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
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object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
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object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
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object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
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}
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static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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const struct MemmapEntry *memmap = ibex_memmap;
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MachineState *ms = MACHINE(qdev_get_machine());
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LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
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MemoryRegion *sys_mem = get_system_memory();
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object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
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&error_abort);
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object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
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&error_abort);
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object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
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/* Boot ROM */
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memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
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memmap[IBEX_DEV_ROM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[IBEX_DEV_ROM].base, &s->rom);
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/* Flash memory */
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memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
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memmap[IBEX_DEV_FLASH].size, &error_fatal);
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memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
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&s->flash_mem);
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/* PLIC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
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/* UART */
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qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
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0, qdev_get_gpio_in(DEVICE(&s->plic),
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IBEX_UART_TX_WATERMARK_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
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1, qdev_get_gpio_in(DEVICE(&s->plic),
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IBEX_UART_RX_WATERMARK_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
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2, qdev_get_gpio_in(DEVICE(&s->plic),
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IBEX_UART_TX_EMPTY_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
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3, qdev_get_gpio_in(DEVICE(&s->plic),
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IBEX_UART_RX_OVERFLOW_IRQ));
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create_unimplemented_device("riscv.lowrisc.ibex.gpio",
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memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
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create_unimplemented_device("riscv.lowrisc.ibex.spi",
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memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
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create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
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memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
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create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
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memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
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create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
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memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
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create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
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memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
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create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
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memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
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create_unimplemented_device("riscv.lowrisc.ibex.aes",
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memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
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create_unimplemented_device("riscv.lowrisc.ibex.hmac",
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memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
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create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
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memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
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create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
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memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
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create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
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memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
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create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
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memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
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create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
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memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
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}
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static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = lowrisc_ibex_soc_realize;
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/* Reason: Uses serial_hds in realize function, thus can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo lowrisc_ibex_soc_type_info = {
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.name = TYPE_RISCV_IBEX_SOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(LowRISCIbexSoCState),
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.instance_init = lowrisc_ibex_soc_init,
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.class_init = lowrisc_ibex_soc_class_init,
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};
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static void lowrisc_ibex_soc_register_types(void)
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{
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type_register_static(&lowrisc_ibex_soc_type_info);
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}
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type_init(lowrisc_ibex_soc_register_types)
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