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12ec8bd51e
The header file hw/arm/arm.h now includes only declarations relating to hw/arm/boot.c functionality. Rename it accordingly, and adjust its header comment. The bulk of this commit was created via perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h In a few cases we can just delete the #include: hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and include/hw/arm/bcm2836.h did not require it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
123 lines
3.5 KiB
C
123 lines
3.5 KiB
C
/*
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* Model of the Xilinx Versal
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*
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* Copyright (c) 2018 Xilinx Inc.
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* Written by Edgar E. Iglesias
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#ifndef XLNX_VERSAL_H
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#define XLNX_VERSAL_H
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#include "hw/sysbus.h"
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#include "hw/arm/boot.h"
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#include "hw/intc/arm_gicv3.h"
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#define TYPE_XLNX_VERSAL "xlnx-versal"
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#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
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#define XLNX_VERSAL_NR_ACPUS 2
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#define XLNX_VERSAL_NR_UARTS 2
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#define XLNX_VERSAL_NR_GEMS 2
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#define XLNX_VERSAL_NR_IRQS 192
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typedef struct Versal {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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struct {
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struct {
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MemoryRegion mr;
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ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
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GICv3State gic;
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} apu;
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} fpd;
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MemoryRegion mr_ps;
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struct {
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/* 4 ranges to access DDR. */
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MemoryRegion mr_ddr_ranges[4];
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} noc;
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struct {
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MemoryRegion mr_ocm;
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struct {
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SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
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SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
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} iou;
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} lpd;
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struct {
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MemoryRegion *mr_ddr;
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uint32_t psci_conduit;
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} cfg;
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} Versal;
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/* Memory-map and IRQ definitions. Copied a subset from
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* auto-generated files. */
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#define VERSAL_GIC_MAINT_IRQ 9
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#define VERSAL_TIMER_VIRT_IRQ 11
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#define VERSAL_TIMER_S_EL1_IRQ 13
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#define VERSAL_TIMER_NS_EL1_IRQ 14
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#define VERSAL_TIMER_NS_EL2_IRQ 10
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#define VERSAL_UART0_IRQ_0 18
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#define VERSAL_UART1_IRQ_0 19
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#define VERSAL_GEM0_IRQ_0 56
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#define VERSAL_GEM0_WAKE_IRQ_0 57
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#define VERSAL_GEM1_IRQ_0 58
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#define VERSAL_GEM1_WAKE_IRQ_0 59
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/* Architecturally reserved IRQs suitable for virtualization. */
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#define VERSAL_RSVD_IRQ_FIRST 111
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#define VERSAL_RSVD_IRQ_LAST 118
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#define MM_TOP_RSVD 0xa0000000U
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#define MM_TOP_RSVD_SIZE 0x4000000
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#define MM_GIC_APU_DIST_MAIN 0xf9000000U
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#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
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#define MM_GIC_APU_REDIST_0 0xf9080000U
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#define MM_GIC_APU_REDIST_0_SIZE 0x80000
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#define MM_UART0 0xff000000U
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#define MM_UART0_SIZE 0x10000
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#define MM_UART1 0xff010000U
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#define MM_UART1_SIZE 0x10000
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#define MM_GEM0 0xff0c0000U
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#define MM_GEM0_SIZE 0x10000
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#define MM_GEM1 0xff0d0000U
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#define MM_GEM1_SIZE 0x10000
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#define MM_OCM 0xfffc0000U
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#define MM_OCM_SIZE 0x40000
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#define MM_TOP_DDR 0x0
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#define MM_TOP_DDR_SIZE 0x80000000U
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#define MM_TOP_DDR_2 0x800000000ULL
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#define MM_TOP_DDR_2_SIZE 0x800000000ULL
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#define MM_TOP_DDR_3 0xc000000000ULL
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#define MM_TOP_DDR_3_SIZE 0x4000000000ULL
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#define MM_TOP_DDR_4 0x10000000000ULL
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#define MM_TOP_DDR_4_SIZE 0xb780000000ULL
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#define MM_PSM_START 0xffc80000U
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#define MM_PSM_END 0xffcf0000U
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#define MM_CRL 0xff5e0000U
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#define MM_CRL_SIZE 0x300000
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#define MM_IOU_SCNTR 0xff130000U
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#define MM_IOU_SCNTR_SIZE 0x10000
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#define MM_IOU_SCNTRS 0xff140000U
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#define MM_IOU_SCNTRS_SIZE 0x10000
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#define MM_FPD_CRF 0xfd1a0000U
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#define MM_FPD_CRF_SIZE 0x140000
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#endif
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