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On some boards, SCC config register CFG0 bit 0 controls whether parts of the board memory map are remapped. Support this with: * a device property scc-cfg0 so the board can specify the initial value of the CFG0 register * an outbound GPIO line which tracks bit 0 and which the board can wire up to provide the remapping Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210504120912.23094-3-peter.maydell@linaro.org
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/*
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* ARM MPS2 SCC emulation
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*
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* Copyright (c) 2017 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the Serial Communication Controller (SCC)
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* block found in most MPS FPGA images.
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*
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* QEMU interface:
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* + sysbus MMIO region 0: the register bank
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* + QOM property "scc-cfg4": value of the read-only CFG4 register
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* + QOM property "scc-aid": value of the read-only SCC_AID register
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* + QOM property "scc-id": value of the read-only SCC_ID register
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* + QOM property "scc-cfg0": reset value of the CFG0 register
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* + QOM property array "oscclk": reset values of the OSCCLK registers
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* (which are accessed via the SYS_CFG channel provided by this device)
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* + named GPIO output "remap": this tracks the value of CFG0 register
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* bit 0. Boards where this bit controls memory remapping should
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* connect this GPIO line to a function performing that mapping.
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* Boards where bit 0 has no special function should leave the GPIO
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* output disconnected.
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*/
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#ifndef MPS2_SCC_H
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#define MPS2_SCC_H
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#include "hw/sysbus.h"
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#include "hw/misc/led.h"
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#include "qom/object.h"
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#define TYPE_MPS2_SCC "mps2-scc"
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OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC)
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struct MPS2SCC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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LEDState *led[8];
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uint32_t cfg0;
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uint32_t cfg1;
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uint32_t cfg2;
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uint32_t cfg4;
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uint32_t cfg5;
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uint32_t cfg6;
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uint32_t cfgdata_rtn;
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uint32_t cfgdata_out;
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uint32_t cfgctrl;
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uint32_t cfgstat;
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uint32_t dll;
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uint32_t aid;
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uint32_t id;
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uint32_t num_oscclk;
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uint32_t *oscclk;
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uint32_t *oscclk_reset;
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uint32_t cfg0_reset;
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qemu_irq remap;
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};
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#endif
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