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		ea9cea93c6
		
	
	
	
	
		
			
			Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-5-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
		
			
				
	
	
		
			51 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			51 lines
		
	
	
		
			1.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * ASPEED Hash and Crypto Engine
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|  *
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|  * Copyright (C) 2021 IBM Corp.
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|  *
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|  * SPDX-License-Identifier: GPL-2.0-or-later
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|  */
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| 
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| #ifndef ASPEED_HACE_H
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| #define ASPEED_HACE_H
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| 
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| #include "hw/sysbus.h"
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| 
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| #define TYPE_ASPEED_HACE "aspeed.hace"
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| #define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400"
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| #define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
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| #define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
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| #define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"
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| 
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| OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
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| 
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| #define ASPEED_HACE_NR_REGS (0x64 >> 2)
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| #define ASPEED_HACE_MAX_SG  256 /* max number of entries */
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| 
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| struct AspeedHACEState {
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|     SysBusDevice parent;
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| 
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|     MemoryRegion iomem;
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|     qemu_irq irq;
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| 
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|     struct iovec iov_cache[ASPEED_HACE_MAX_SG];
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|     uint32_t regs[ASPEED_HACE_NR_REGS];
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|     uint32_t total_req_len;
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|     uint32_t iov_count;
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| 
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|     MemoryRegion *dram_mr;
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|     AddressSpace dram_as;
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| };
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| 
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| 
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| struct AspeedHACEClass {
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|     SysBusDeviceClass parent_class;
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| 
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|     uint32_t src_mask;
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|     uint32_t dest_mask;
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|     uint32_t key_mask;
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|     uint32_t hash_mask;
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| };
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| 
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| #endif /* ASPEED_HACE_H */
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