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The SSE-300 has a new register block CPU<N>_PWRCTRL. There is one instance of this per CPU in the system (so just one for the SSE-300), and as well as the usual CIDR/PIDR ID registers it has just one register, CPUPWRCFG. This register allows the guest to configure behaviour of the system in power-down and deep-sleep states. Since QEMU does not model those, we make the register a dummy reads-as-written implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-21-peter.maydell@linaro.org
41 lines
958 B
C
41 lines
958 B
C
/*
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* ARM SSE CPU PWRCTRL register block
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*
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* Copyright (c) 2021 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "CPU<N>_PWRCTRL block" which is part of the
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* Arm Corstone SSE-300 Example Subsystem and documented in
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* https://developer.arm.com/documentation/101773/0000
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*
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* QEMU interface:
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* + sysbus MMIO region 0: the register bank
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*/
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#ifndef HW_MISC_ARMSSE_CPU_PWRCTRL_H
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#define HW_MISC_ARMSSE_CPU_PWRCTRL_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_ARMSSE_CPU_PWRCTRL "armsse-cpu-pwrctrl"
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OBJECT_DECLARE_SIMPLE_TYPE(ARMSSECPUPwrCtrl, ARMSSE_CPU_PWRCTRL)
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struct ARMSSECPUPwrCtrl {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t cpupwrcfg;
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};
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#endif
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