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1f85d74ac5
Add a function that generates a Virtual I/O Translation table (VIOT), describing the topology of paravirtual IOMMUs. The table is created if a virtio-iommu device is present. It contains a virtio-iommu node and PCI Range nodes for endpoints managed by the IOMMU. By default, a single node describes all PCI devices. When passing the "default_bus_bypass_iommu" machine option and "bypass_iommu" PXB option, only buses that do not bypass the IOMMU are described by PCI Range nodes. Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-Id: <20211026182024.2642038-2-jean-philippe@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
/*
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* ACPI Virtual I/O Translation table implementation
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/acpi/viot.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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struct viot_pci_ranges {
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GArray *blob;
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size_t count;
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uint16_t output_node;
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};
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/* Build PCI range for a given PCI host bridge */
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static int build_pci_range_node(Object *obj, void *opaque)
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{
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struct viot_pci_ranges *pci_ranges = opaque;
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GArray *blob = pci_ranges->blob;
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if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
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PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
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if (bus && !pci_bus_bypass_iommu(bus)) {
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int min_bus, max_bus;
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pci_bus_range(bus, &min_bus, &max_bus);
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/* Type */
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build_append_int_noprefix(blob, 1 /* PCI range */, 1);
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/* Reserved */
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build_append_int_noprefix(blob, 0, 1);
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/* Length */
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build_append_int_noprefix(blob, 24, 2);
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/* Endpoint start */
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build_append_int_noprefix(blob, PCI_BUILD_BDF(min_bus, 0), 4);
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/* PCI Segment start */
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build_append_int_noprefix(blob, 0, 2);
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/* PCI Segment end */
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build_append_int_noprefix(blob, 0, 2);
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/* PCI BDF start */
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build_append_int_noprefix(blob, PCI_BUILD_BDF(min_bus, 0), 2);
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/* PCI BDF end */
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build_append_int_noprefix(blob, PCI_BUILD_BDF(max_bus, 0xff), 2);
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/* Output node */
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build_append_int_noprefix(blob, pci_ranges->output_node, 2);
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/* Reserved */
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build_append_int_noprefix(blob, 0, 6);
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pci_ranges->count++;
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}
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}
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return 0;
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}
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/*
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* Generate a VIOT table with one PCI-based virtio-iommu that manages PCI
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* endpoints.
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*
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* Defined in the ACPI Specification (Version TBD)
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*/
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void build_viot(MachineState *ms, GArray *table_data, BIOSLinker *linker,
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uint16_t virtio_iommu_bdf, const char *oem_id,
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const char *oem_table_id)
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{
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/* The virtio-iommu node follows the 48-bytes header */
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int viommu_off = 48;
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AcpiTable table = { .sig = "VIOT", .rev = 0,
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.oem_id = oem_id, .oem_table_id = oem_table_id };
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struct viot_pci_ranges pci_ranges = {
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.output_node = viommu_off,
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.blob = g_array_new(false, true /* clear */, 1),
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};
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/* Build the list of PCI ranges that this viommu manages */
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object_child_foreach_recursive(OBJECT(ms), build_pci_range_node,
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&pci_ranges);
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/* ACPI table header */
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acpi_table_begin(&table, table_data);
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/* Node count */
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build_append_int_noprefix(table_data, pci_ranges.count + 1, 2);
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/* Node offset */
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build_append_int_noprefix(table_data, viommu_off, 2);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 8);
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/* Virtio-iommu node */
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/* Type */
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build_append_int_noprefix(table_data, 3 /* virtio-pci IOMMU */, 1);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 1);
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/* Length */
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build_append_int_noprefix(table_data, 16, 2);
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/* PCI Segment */
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build_append_int_noprefix(table_data, 0, 2);
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/* PCI BDF number */
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build_append_int_noprefix(table_data, virtio_iommu_bdf, 2);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 8);
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/* PCI ranges found above */
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g_array_append_vals(table_data, pci_ranges.blob->data,
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pci_ranges.blob->len);
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g_array_free(pci_ranges.blob, true);
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acpi_table_end(linker, &table);
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}
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