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a8d2532645
No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
363 lines
12 KiB
C
363 lines
12 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu.h"
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#include "cpu_loop-common.h"
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/***********************************************************/
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/* CPUX86 core interface */
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uint64_t cpu_get_tsc(CPUX86State *env)
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{
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return cpu_get_host_ticks();
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}
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static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
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int flags)
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{
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unsigned int e1, e2;
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uint32_t *p;
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e1 = (addr << 16) | (limit & 0xffff);
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e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
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e2 |= flags;
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p = ptr;
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p[0] = tswap32(e1);
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p[1] = tswap32(e2);
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}
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static uint64_t *idt_table;
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#ifdef TARGET_X86_64
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static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
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uint64_t addr, unsigned int sel)
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{
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uint32_t *p, e1, e2;
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e1 = (addr & 0xffff) | (sel << 16);
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e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
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p = ptr;
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p[0] = tswap32(e1);
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p[1] = tswap32(e2);
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p[2] = tswap32(addr >> 32);
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p[3] = 0;
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}
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/* only dpl matters as we do only user space emulation */
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static void set_idt(int n, unsigned int dpl)
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{
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set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
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}
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#else
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static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
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uint32_t addr, unsigned int sel)
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{
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uint32_t *p, e1, e2;
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e1 = (addr & 0xffff) | (sel << 16);
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e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
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p = ptr;
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p[0] = tswap32(e1);
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p[1] = tswap32(e2);
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}
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/* only dpl matters as we do only user space emulation */
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static void set_idt(int n, unsigned int dpl)
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{
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set_gate(idt_table + n, 0, dpl, 0, 0);
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}
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#endif
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void cpu_loop(CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr;
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abi_ulong pc;
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abi_ulong ret;
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target_siginfo_t info;
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for(;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch(trapnr) {
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case 0x80:
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/* linux syscall from int $0x80 */
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ret = do_syscall(env,
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env->regs[R_EAX],
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env->regs[R_EBX],
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env->regs[R_ECX],
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env->regs[R_EDX],
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env->regs[R_ESI],
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env->regs[R_EDI],
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env->regs[R_EBP],
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0, 0);
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if (ret == -TARGET_ERESTARTSYS) {
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env->eip -= 2;
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} else if (ret != -TARGET_QEMU_ESIGRETURN) {
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env->regs[R_EAX] = ret;
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}
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break;
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#ifndef TARGET_ABI32
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case EXCP_SYSCALL:
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/* linux syscall from syscall instruction */
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ret = do_syscall(env,
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env->regs[R_EAX],
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env->regs[R_EDI],
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env->regs[R_ESI],
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env->regs[R_EDX],
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env->regs[10],
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env->regs[8],
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env->regs[9],
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0, 0);
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if (ret == -TARGET_ERESTARTSYS) {
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env->eip -= 2;
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} else if (ret != -TARGET_QEMU_ESIGRETURN) {
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env->regs[R_EAX] = ret;
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}
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break;
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#endif
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case EXCP0B_NOSEG:
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case EXCP0C_STACK:
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info.si_signo = TARGET_SIGBUS;
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info.si_errno = 0;
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info.si_code = TARGET_SI_KERNEL;
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info._sifields._sigfault._addr = 0;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP0D_GPF:
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/* XXX: potential problem if ABI32 */
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#ifndef TARGET_X86_64
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if (env->eflags & VM_MASK) {
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handle_vm86_fault(env);
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} else
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#endif
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{
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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info.si_code = TARGET_SI_KERNEL;
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info._sifields._sigfault._addr = 0;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP0E_PAGE:
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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if (!(env->error_code & 1))
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info.si_code = TARGET_SEGV_MAPERR;
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else
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info.si_code = TARGET_SEGV_ACCERR;
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info._sifields._sigfault._addr = env->cr[2];
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP00_DIVZ:
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#ifndef TARGET_X86_64
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if (env->eflags & VM_MASK) {
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handle_vm86_trap(env, trapnr);
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} else
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#endif
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{
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/* division by zero */
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info.si_signo = TARGET_SIGFPE;
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info.si_errno = 0;
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info.si_code = TARGET_FPE_INTDIV;
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info._sifields._sigfault._addr = env->eip;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP01_DB:
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case EXCP03_INT3:
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#ifndef TARGET_X86_64
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if (env->eflags & VM_MASK) {
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handle_vm86_trap(env, trapnr);
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} else
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#endif
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{
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info.si_signo = TARGET_SIGTRAP;
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info.si_errno = 0;
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if (trapnr == EXCP01_DB) {
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info.si_code = TARGET_TRAP_BRKPT;
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info._sifields._sigfault._addr = env->eip;
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} else {
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info.si_code = TARGET_SI_KERNEL;
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info._sifields._sigfault._addr = 0;
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}
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP04_INTO:
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case EXCP05_BOUND:
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#ifndef TARGET_X86_64
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if (env->eflags & VM_MASK) {
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handle_vm86_trap(env, trapnr);
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} else
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#endif
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{
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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info.si_code = TARGET_SI_KERNEL;
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info._sifields._sigfault._addr = 0;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP06_ILLOP:
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_ILLOPN;
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info._sifields._sigfault._addr = env->eip;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_DEBUG:
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info.si_signo = TARGET_SIGTRAP;
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info.si_errno = 0;
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info.si_code = TARGET_TRAP_BRKPT;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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pc = env->segs[R_CS].base + env->eip;
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EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
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(long)pc, trapnr);
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abort();
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}
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process_pending_signals(env);
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}
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}
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
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env->hflags |= HF_PE_MASK | HF_CPL_MASK;
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if (env->features[FEAT_1_EDX] & CPUID_SSE) {
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env->cr[4] |= CR4_OSFXSR_MASK;
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env->hflags |= HF_OSFXSR_MASK;
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}
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#ifndef TARGET_ABI32
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/* enable 64 bit mode if possible */
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if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
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fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
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exit(EXIT_FAILURE);
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}
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env->cr[4] |= CR4_PAE_MASK;
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env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
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env->hflags |= HF_LMA_MASK;
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#endif
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/* flags setup : we activate the IRQs by default as in user mode */
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env->eflags |= IF_MASK;
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/* linux register setup */
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#ifndef TARGET_ABI32
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env->regs[R_EAX] = regs->rax;
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env->regs[R_EBX] = regs->rbx;
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env->regs[R_ECX] = regs->rcx;
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env->regs[R_EDX] = regs->rdx;
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env->regs[R_ESI] = regs->rsi;
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env->regs[R_EDI] = regs->rdi;
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env->regs[R_EBP] = regs->rbp;
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env->regs[R_ESP] = regs->rsp;
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env->eip = regs->rip;
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#else
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env->regs[R_EAX] = regs->eax;
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env->regs[R_EBX] = regs->ebx;
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env->regs[R_ECX] = regs->ecx;
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env->regs[R_EDX] = regs->edx;
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env->regs[R_ESI] = regs->esi;
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env->regs[R_EDI] = regs->edi;
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env->regs[R_EBP] = regs->ebp;
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env->regs[R_ESP] = regs->esp;
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env->eip = regs->eip;
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#endif
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/* linux interrupt setup */
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#ifndef TARGET_ABI32
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env->idt.limit = 511;
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#else
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env->idt.limit = 255;
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#endif
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env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
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PROT_READ|PROT_WRITE,
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MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
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idt_table = g2h(env->idt.base);
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set_idt(0, 0);
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set_idt(1, 0);
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set_idt(2, 0);
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set_idt(3, 3);
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set_idt(4, 3);
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set_idt(5, 0);
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set_idt(6, 0);
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set_idt(7, 0);
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set_idt(8, 0);
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set_idt(9, 0);
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set_idt(10, 0);
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set_idt(11, 0);
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set_idt(12, 0);
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set_idt(13, 0);
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set_idt(14, 0);
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set_idt(15, 0);
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set_idt(16, 0);
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set_idt(17, 0);
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set_idt(18, 0);
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set_idt(19, 0);
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set_idt(0x80, 3);
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/* linux segment setup */
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{
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uint64_t *gdt_table;
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env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
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PROT_READ|PROT_WRITE,
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MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
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env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
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gdt_table = g2h(env->gdt.base);
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#ifdef TARGET_ABI32
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write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
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(3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
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#else
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/* 64 bit code segment */
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write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
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DESC_L_MASK |
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(3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
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#endif
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write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
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(3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
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}
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cpu_x86_load_seg(env, R_CS, __USER_CS);
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cpu_x86_load_seg(env, R_SS, __USER_DS);
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#ifdef TARGET_ABI32
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cpu_x86_load_seg(env, R_DS, __USER_DS);
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cpu_x86_load_seg(env, R_ES, __USER_DS);
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cpu_x86_load_seg(env, R_FS, __USER_DS);
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cpu_x86_load_seg(env, R_GS, __USER_DS);
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/* This hack makes Wine work... */
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env->segs[R_FS].selector = 0;
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#else
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cpu_x86_load_seg(env, R_DS, 0);
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cpu_x86_load_seg(env, R_ES, 0);
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cpu_x86_load_seg(env, R_FS, 0);
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cpu_x86_load_seg(env, R_GS, 0);
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#endif
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}
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