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8063396bf3
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
128 lines
2.8 KiB
C
128 lines
2.8 KiB
C
/*
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* QEMU I/O port 0x92 (System Control Port A, to handle Fast Gate A20)
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "qemu/osdep.h"
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#include "sysemu/runstate.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/i386/pc.h"
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#include "trace.h"
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#include "qom/object.h"
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OBJECT_DECLARE_SIMPLE_TYPE(Port92State, PORT92)
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struct Port92State {
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ISADevice parent_obj;
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MemoryRegion io;
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uint8_t outport;
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qemu_irq a20_out;
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};
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static void port92_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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Port92State *s = opaque;
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int oldval = s->outport;
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trace_port92_write(val);
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s->outport = val;
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qemu_set_irq(s->a20_out, (val >> 1) & 1);
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if ((val & 1) && !(oldval & 1)) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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}
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static uint64_t port92_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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Port92State *s = opaque;
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uint32_t ret;
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ret = s->outport;
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trace_port92_read(ret);
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return ret;
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}
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static const VMStateDescription vmstate_port92_isa = {
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.name = "port92",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(outport, Port92State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void port92_reset(DeviceState *d)
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{
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Port92State *s = PORT92(d);
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s->outport &= ~1;
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}
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static const MemoryRegionOps port92_ops = {
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.read = port92_read,
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.write = port92_write,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void port92_initfn(Object *obj)
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{
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Port92State *s = PORT92(obj);
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memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
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s->outport = 0;
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qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
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}
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static void port92_realizefn(DeviceState *dev, Error **errp)
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{
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ISADevice *isadev = ISA_DEVICE(dev);
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Port92State *s = PORT92(dev);
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isa_register_ioport(isadev, &s->io, 0x92);
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}
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static void port92_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = port92_realizefn;
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dc->reset = port92_reset;
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dc->vmsd = &vmstate_port92_isa;
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/*
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* Reason: unlike ordinary ISA devices, this one needs additional
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* wiring: its A20 output line needs to be wired up with
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* qdev_connect_gpio_out_named().
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo port92_info = {
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.name = TYPE_PORT92,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(Port92State),
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.instance_init = port92_initfn,
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.class_init = port92_class_initfn,
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};
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static void port92_register_types(void)
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{
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type_register_static(&port92_info);
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}
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type_init(port92_register_types)
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